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Need help on Remote system upgrade of CYCLONE III..urgent

Altera_Forum
Honored Contributor II
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Hi all, 

 

I have a cyclone III device and a serial configuration device(EPCS flash). 

I have a factory image (SOF1) programmed at the EPCS flash address 0x00000000. 

I have an application image(SOF2) programmed at the EPCS flash address 0x000A0000. 

 

Whenever i boot up, the factory image (SOF1) loads in the FPGA. The software application of the SOF1 triggers reconfiguration at the EPCS flash address 0x000A0000 to configure the FPGA with SOF2. 

Assume that SOF2 is now configured and its corresponding software application is running. 

Now at this point i need to reset back to factory image without power cycle.  

How is this possible?  

which registers should i access to hit a reset to the factory image? 

As per the altera document once SOF2 is loaded we wont be in the factory mode and hence i guess i cannot trigger reconfiguration for the SOF1 at 0x00000000. If this is the case how can i reset back to SOF1 without powercycle. 

 

Please help. 

 

Thanks a lot in advance
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Altera_Forum
Honored Contributor II
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SOF1 is located directly after the fpga image, so its starting adr depends upond the lengtf of your fpga image and this may change depending upon image compression 

so SOF does not start at 0x0 as the fpga downloaded from epcs starts at 0x0
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Altera_Forum
Honored Contributor II
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Thanks a lot for the reply MSchmitt..... 

Sorry i dint get you, My SOF1 is the factory FPGA image itself which is flashed at the EPCS flash address 0x00000000. Hence whenever powercycle is given, The SOF1 factory image loads, a software application of the SOF1 is then loaded by the bootloader. This software application of mine triggers a reconfiguration at the EPCS flash address 0x000A0000 where my Application FPGA image(SOF2) is present. After reconfiguration the SOF2 is configured in the FPGA, then an software application of SOF2 is loaded in RAM. In this software application i want to write a logic to configure back the SOF1 factory FPGA image. How can i do this?
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