clock gating issue

[Altera_Forum]

Hello All 

 I am using quartus for stratix3 device. I have few clock gating module in desung and switch on the Auto_Gate_Conversion in quartus software to remove them. I am using timequest and also generated sdc file. The quartus does not convert the clock gate cell. In the map report its written:   ---+ ; Gated Clock Conversion Details ; ----+ ; Gated Clock ; Base Clock ; Converted to Clock Enable ; Reason not Converted ; ---+ ; phy_fe_unit_wrap_ctrl|phy_fe_unit_wrap_ctrl_i|dan_gclk:dan_gclk_i|gclk ; phy_fe_clk ; No ; Found register phy_fe_tx_cfr|phy_fe_tx_cfr_i|cfr_dout_real[15] fed by the gated clock tree has in-use clock enable ; -+   Can someone explain me this report? How do i solve this problem?   Thanks, Rami