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Altera_Forum
Honored Contributor I
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Need help with external SRAM read/write

Hi, 

 

I am a newbie to the FPGA. Currently, I am trying to redesign a FPGA to include the FFT. The FPGA chip used is Cyclone II family EP2C8F256I8. The microprocessor used is a ARM9 LPC3180. The current design uses FPGA on-chip RAM (162 kB) to store the time-domain data acquired (4096 by 16 bit data/channel, 2 channels) and the data is transferred through a SPI bus controlled by the ARM9 firmware. To include the FFT, we can no longer store the data in the on-chip RAM, since that will be used to pipeline the FFT core. A 512-point FFT consumes 88 K RAM bits. There's a 64k * 16bit SRAM chip on the board which can be accessed through the FPGA. My idea is to cache the data into the SRAM and then we do the FFT and cache the results also into the SRAM. My question is if we want to read the data from SRAM through the FPGA and transfer them via the SPI bus controlled by the ARM9, do we need to first put the data back into the on-chip RAM? The LPC3180 has a 64*16bit FIFO associated with the SPI bus.  

 

Thanks, 

 

-Roger
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Altera_Forum
Honored Contributor I
16 Views

Typically such FIFOs as you mention on the Arm are used to allow efficient programming and increase the transfer rate on the SPI line. 

So no primary influence for your implementation if it should "just work". It might get of interest when speed is topic. 

 

It depends a little on how you readout the data using the SPI bus. The question you have to ask is: When the FPGA gets the command to respond with SRAM data, how much time (clock cycles on FPGA, clock cycles on SPI bus) is needed until the bits are available in a register in the FPGA. If it is fast enough, it could be possible to respond in time. If not you could introduce a data delay of e.g. one SRAM value by setting the first response to e.g. always 0x0, and then the data. 

So to sum up: It depends on timing (clocks involved) and the protocol you use on the SPI bus.