Need help with timing constraints/closure for an EMIF design

[BKB]

Hi,

We have a design with 2 EMIFs with user clock at 200Mhz and it had more than 3.5 ns timing failure when the RS8 logic was added. With design changes and iterations the design still fails by 2ns.

The fit.fastforward report makes some suggestions to add register stages which I have passed on the designers and waiting response.

The report also makes suggestions to change asynchronous clears to synchronous clears. I haven't made the changes in the code but I set it in qsf

set_global_assignment -name FORCE_SYNCH_CLEAR ON

But the the fit.fastforward report mentions that the asynchronous clear are not converted to synchronous. Please review the review report and help with timing closure.

Best,

BB

[BKB]

Thanks Richard. No, I don't have any specific inquiry except that if you have a script or function that can accept a file and convert all asynchronous to synchronous reset, that would help tremendously. I am having issues with the script I am trying, even with chatgpt. 

you can transition this tread to community support. 

Best, 

Bharat

[RichardTanSY_Altera]

Thank you for the confirmation. Unfortunately, I don't have a script available that automatically converts async to sync. Users will need to write their own scripts to suit their specific design requirements.

With that, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan

[BKB]

Hi Richard, 

Thanks for your help past few weeks. You can close this request. 

Best, 

Bharat