Need some help to use altdq and altdqs megafunction.

[Altera_Forum]

Hi,  

  I am working on memory controller. In that data received from memory is edge aligned with clock. I want to give phase shift of incoming clock to 90 degree so that I can receive data center aligned. Can I use altdq and altdqs mega function to provide 90 degree phase shift of incoming clock?  I am using cyclone IVe device.   Thanks in advance.  Regards,  Krupesh

[Altera_Forum]

So you want to make your own memory Phy? Most (if not all) of the top reputation holders will warn you that is a challenge. I too believe it is. 

To answer your question: Yes, using altdq and altdqs is one way to go.  Now If you are using altdq and altdqs you are getting near the complexity of Altera's Altmem_Phy.  There are other solutions depending on your requirements on the memory speed and number of chips, or DIMMs, involved. Is there a particular reason you want to roll your own?

[Altera_Forum]

Cyclone II did include a delay-circuit for DQS. Cyclone III and IV do not, so you have to ensure this delay by routing/constraints. 

 BTW: I think, the Altera-phy does rely on the DLL in the DDR(2)-memories (not in Mobile DDR!) which ensures that the DQS-phase is close to the memory-clock-phase. Additionally it fine-adjusts the capture-clock with the phase-shift-functionality of the FPGA-PLL by calibration. As far as I know, it does not use DQS for capturing the data.  Thomas

[Altera_Forum]

Indeed, I checked this today and it is new to me , in Cyclone III and IV DQS is only used to write out data (as required by the DDR2 devices) and reading is done with a separate capture clock in their Altmem-Phy. So they rely on the Tac specification of the DDR2 device, Tac is referenced to the incoming clock at the DDR2 device.  

The major drawback of using Altmem-Phy though is that it is so big, Altera's memory controller with Altmem-Phy uses 2450 LEs in a CycloneIII, or half of the smallest EP3C5 device. And while compiling it spits out lots of warnings, confusing the user wondering whether it is his fault?

[Altera_Forum]

Thanks for replying in such short time. 

 I forgot to tell you that I am designing nand flash controller and not DDR controller. I instantiated altdq and altdqs megafunction in my design. I did not get any phase shift in my incoming clock. I think altdqs megafunction is little bit confusing. In that one NOTE is there USE INPUT DELAY FROM DUAL Purpose Clock Pin assignment in the Assignment Editor to set DQS clock delay. I assigned different value for dqs pin but I did not get any phase shift.  So please help me if you have any idea regarding this issue.  Regards,  Krupesh

[Altera_Forum]

What FLASH device(s)? And which ALtera device? 

 I checked the Open NAND Flash Interface Specification, Revision 2.3. If you are using the Flash device in source synchronous mode you do have a DDR interface for writing and reading data. From the timing it looks like you have to use the DQS to read data into the FPGA, so you will need a DLL in your FPGA device, limiting the choice somewhat.

[Altera_Forum]

I am using onfi compatible nand flash memory and I am using cycloneIV E fpga device.Does altdqs mega function has inbuilt DLL? 

 Thanks and Regards, Krupesh

[Altera_Forum]

As TEntner learned us, Cyclone IV devices don't have a DLL in the DQS block. 

The ONFI spec allows a 3 to 20 nsec delay for sending DQS back on read, which means you cannot relate the incoming DQS to any clock in the FPGA, in other words: it seems you have to use either CycloneII, StratixII , StratixIII ... At what speed do you want / need to run the Flash memory?