Timing problem

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Timing problem

831 Views

Hi,

I wrote a code that works very well in ModelSim but when I’m trying to burn the code on the MAX 2 CPLD (EPM2210F256I5) the software is not running as expected (and I think it even stuck …).

On the Processing labels I get info about tco= 10.010nsec, tsu= 7.470nsec, th= -14.413nsec clock setup: 78.46MHz (I’m working with 10MHz clock).

Is this could be the code problem? What should I do?

Idan

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.