New to Modelsim, and a beginner question

[Altera_Forum]

So i try using modelsim altera to simulate my simple verilog code, i recently have had to switch to altera so i am very new. 

 I have written a simple 4 bit adder and i want to simulate it,   module chos(;  reg[3:0] a,b; reg cin; wire[3:0] sum; wire cout;  full_adder_4bit dut(a,b,cin,sum,cout);  initial begin  a = 4'b0000; b = 4'b0000; cin = 1'b0; # 50; a = 4'b0101; b = 4'b1010; # 50; a = 4'b1111; b = 4'b0001; # 50; a = 4'b0000; b = 4'b1111; cin = 1'b1; # 50; a = 4'b0110; b = 4'b0001; end  endmodule  ** you can be sure that my full-adder_4bit module is correct. anyway when i try to simulate it . it says the top partition has no logic in it.  How do you write a testbench, such that you can get something showing up in ModelSim?

[Altera_Forum]

I tried your testbench code and it works fine with my 4-bit adder module. 

 All you need to do, is making a new projekt in modelsim, add the design and the testbench file, compile them, and start the simulation.

[Altera_Forum]

Did you use quartus II>? i am using quartus II and then it migrates to modelsim :(

[Altera_Forum]

In Quartus first make the designe the Top-Level Entity! 

 After that you have to add the testbench in the projekt-settings.  Go: Assignments\Settings -> EDA Tools Settings -> Simulation in tht page check the Compile Testbench at the NativeLink Settings tab. There you add your testbench file, and i hope it will run properly ;)