Re: Nios II CPU with debug module not detected

Altera_Forum · ‎07-28-2009

Hi

I am new to Altera's design flow, so please bear with me.

I have a DE3 board from Terasic with the Stratix III EP3SL150F1152C2N FPGA. Using SOPC builder, I created a system containing a Nios II processor (with a JTAG debug module), a JTAG UART module, and an on-chip memory. I also added some logic in order to drive the LEDs. I connected one of the board's buttons to the resetN port of the system generated by SOPC-builder

Now when I downloaded the SOF file, the LEDs work properly, but jtagconfig returns only


1) USB-Blaster 
  121020DD

The jtagconfig manual says that two more lines (one for JTAG config and one for JTAG debug module) must be printed, but that never happens. Now, if I try to use nios2-download or nios2-ide (after specifying the correct ptf file), it gives an error:


There are no Nios II CPUs with debug modules available which match the values
specified.  Please check that your PLD is correctly configured, downloading a
new SOF file if necessary.

If I use nios2-terminal it returns an error saying


nios2-terminal: There are no JTAG UARTs available which match the --device and
nios2-terminal: --instance options you provided.

I tried resetting the sytem (tried issuing these commands, when the button is pressed, etc). But everytime I get the same outputs/errors.

It looks I am missing something trivial. Do I have to do some pin assignments for JTAG UART (currently they seem to be done magically through the JTAG link)? Is the problem related to licensing? I do not know if I have the NIOS II IP core license, License setup in quartus shows a "NIOS II Embedded Processor Encrypted Output". Is that not enough? I have subscription licenses for Quartus II.

Thanks

Altera_Forum · ‎07-28-2009

When you downloaded sof file to FPGA, ¿does a window with a cancel button appear saying: "opencore plus status:click cancel to stop using opencoreplus Ip Time remaining unlimited."? If it does, don cancel it.

Altera_Forum · ‎07-28-2009

No, I do not get any popups when I download the SOF file using the programmer tool. My host computer runs Ubuntu Linux btw.

Altera_Forum · ‎08-11-2009

Hi all, I've been getting the message:

"There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary."

when trying to download my NIOS application to my hardware.

I've figured out the reason for my specific problem so thought I'd let you know in case it's helpful to anyone else:

The problem originates in Quartus not the Nios system.

I had been keeping copies of earlier .ptf files in my QuartusII project design directory, just renamed in case I wanted them back later.

The problem seems to be that when I compile my Quartus project, the compiler finds the other .ptf files and decides to alter the jtag chain details which results in the NIOS debug operation failing later.

I deleted the project .ptf and .sof files and renamed the file extension on all my old .ptf files to something else e.g. name.ptfbak. Generate the SOPC Builder component and compile the Quartus project again so it generates new .ptf and .sof files and and this problem goes away when you use them in the NIOS project.

Altera_Forum · ‎11-20-2009

@tgtg,

I am seeing the same problem with the same error message on nios2-download. I am also running ubuntu (9.10). What is strange is that I had this thing working the other day with a precompiled .sof and matching linux-for-NIOSII image. Now it doesn't seem to be working.

Did you ever figure this out?

Altera_Forum · ‎11-20-2009

Seems a bit strange but I hope this helps:

Have you been saving old copies of .ptf files and just renaming them for example to keep as a backup?

The solution to my problem seemed to be not to have any copies of .ptf files hanging around in the design directory, other than the one I want. Even if I renamed a copied file the IDE seemed to get confused by the presence of another .ptf, so change .ptf to .ptftemp or something - it all miraculously got better afterwards.

As a general principle I now apply this to .ptf, .sof and .sopcinfo files because getting these mixed up and using the wrong copy leads to all sorts of chaos.

Altera_Forum · ‎07-14-2010

I am using Lucid Lynx an the altera 8.1 toolchain. The totaly toolchain worked pretty good when I set it up. But then I got the problem with:

"There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary."

It also doenst help to create a new project and it also doesnt help to delte all file except:

in the quartus design dir.

Its really strange. Because it also doesnt work to auto detect after I program the target with the standard stratixIII_3sl150_dev_pfl.sof file from altera. It just returns me an empty target.

Looks like the USB connection only works one-way.

btw.

When I run this script at start up:# !/bin/sh

sudo mount --bind /dev/bus /proc/bus

sudo ln -s /sys/kernel/debug/usb/devices /proc/bus/usb/devices

sudo /opt/altera8.1/quartus/bin/jtagd

sudo /opt/altera8.1/quartus/bin/jtagconfig

read -p "Press enter to finish"

(Sometimes) I have to kill a jtagd process before. But the jtagd process ist not running after running the script.

Where is my problem? Can somebody help me?

PS: Even if I flash the correct design under windows it doesnt help(Not possible to download elf files)

PPS: Take a look into the zip file to get an screenshot from the terminal

PPS: I think that the USB-Blaster gets detected but not the FPGA Chip

Altera_Forum · ‎08-11-2010

i used the same script to mount the USB-BLASTER and then when tried to use nios2-flash-programmer the same problem appeared, "There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.",

and with this simple step it got solved (worked for the version of altera software 10.0 on Ubuntu lucid lynx)

what i did was running the script (it only runned when i wrote all the directory) for example in my case was:

bighead@bighead-laptop:~$'/home/bighead/altera/10.0/nios2eds/nios2_command_shell.sh'

and after that it printed

------------------------------------------------

Altera Nios2 Command Shell [GCC 4]

Version 10.0, Build 218

------------------------------------------------

and then everything stays like a normal gnome-terminal, the diference now is that the bin aplications like nios2-flash-programer detects the debug hardware and work(obviusly you have to configure the FPGA with DE1-NIOS.sof in my case that comes with the board demostration circuits)

even using the gui for the flash programmer it works (because it wasnt detecting it either)

Altera_Forum · ‎12-24-2010

--- Quote Start ---

When you downloaded sof file to FPGA, ¿does a window with a cancel button appear saying: "opencore plus status:click cancel to stop using opencoreplus Ip Time remaining unlimited."? If it does, don cancel it.

--- Quote End ---

Hi'

I do also get the same error message with a dsp builder design which consists of two Avalon Memory Mapped Slave blocks. I did all the pins assignments and just dont know what to do next. The funny thing is when I use a simple SOPC design with the "hello_world.c" code, it works witout any problem on IDE.

So what could be the issue with the DSP builder design?

Please help...

Altera_Forum · ‎08-29-2011

i m facing the poblem. can u please guide me

Altera_Forum · ‎03-09-2013

I had this problem couple of days ago, i just had to delete the .SOF file in the project's directory (quartus not the monitoring project). and then i've recompiled the quartus project to generate the file again. no problems occured with the second regenerated .SOF file. let me know if this helps