Nios2 Statistical Timing Analysis

[Altera_Forum]

Hi I have a Nios 2 based design on which I would like to perform statistical timing analysis using Prime Time or some custom flow. The problem is that the nios2 designs are encrypted so i cant push the, through the regular synopsis flow.  

The best I have come up with so far is make the quartus tool output a .vo file, can i use that to resynthesize the circuit using the synopsis flow.   Basically i would love to have the gate level netlist in terms of a simple library than altera fpga primitives. I am a grad student and our university shouldnt have a problem in getting the required licenses.  Thanks

[Altera_Forum]

K simpler question, can Nios 2 Embedded processors be used only with altera boards. All these third party eda support that quartus has, does it work for the nios-2 core as well.  

 I think i have all the licenses, my .soc files are not time limited and i dont get any warnings on using eda_netlist_writer either. I have written out a .vo file using it, but i am not sure if the netlist has the nios2 processor also included.   Someone please help or atleast give me a pointer.