Nios2 data cache with 32-byte burst error

[Altera_Forum]

I took our hardware guy's FPGA (cyclone 2) with Nios2 processor & simply added a data cache with burst (32 bytes), size 512. 

It generated OK with SOPC builder (version 9.1 quartus II tools) but in quartus, it errors with...   Info: Elaborating entity "g110_core_burst_18_upstream_arbitrator" for hierarchy "g110_core:inst|g110_core_burst_18_upstream_arbitrator:the_g110_core_burst_18_upstream" Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value Info: Elaborating entity "burstcount_fifo_for_g110_core_burst_18_upstream_module" for hierarchy "g110_core:inst|g110_core_burst_18_upstream_arbitrator:the_g110_core_burst_18_upstream|burstcount_fifo_for_g110_core_burst_18_upstream_module:burstcount_fifo_for_g110_core_burst_18_upstream" Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value Info: Elaborating entity "rdv_fifo_for_cpu_data_master_to_g110_core_burst_18_upstream_module" for hierarchy "g110_core:inst|g110_core_burst_18_upstream_arbitrator:the_g110_core_burst_18_upstream|rdv_fifo_for_cpu_data_master_to_g110_core_burst_18_upstream_module:rdv_fifo_for_cpu_data_master_to_g110_core_burst_18_upstream" Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value Info: Elaborating entity "g110_core_burst_18_downstream_arbitrator" for hierarchy "g110_core:inst|g110_core_burst_18_downstream_arbitrator:the_g110_core_burst_18_downstream" Warning: Using design file g110_core_burst_18.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: g110_core_burst_18-europa Info: Found entity 1: g110_core_burst_18 Info: Elaborating entity "g110_core_burst_18" for hierarchy "g110_core:inst|g110_core_burst_18:the_g110_core_burst_18" Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value Info: Elaborating entity "g110_core_burst_19_upstream_arbitrator" for hierarchy "g110_core:inst|g110_core_burst_19_upstream_arbitrator:the_g110_core_burst_19_upstream" Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value Info: Elaborating entity "burstcount_fifo_for_g110_core_burst_19_upstream_module" for hierarchy "g110_core:inst|g110_core_burst_19_upstream_arbitrator:the_g110_core_burst_19_upstream|burstcount_fifo_for_g110_core_burst_19_upstream_module:burstcount_fifo_for_g110_core_burst_19_upstream" Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value Info: Elaborating entity "rdv_fifo_for_cpu_data_master_to_g110_core_burst_19_upstream_module" for hierarchy "g110_core:inst|g110_core_burst_19_upstream_arbitrator:the_g110_core_burst_19_upstream|rdv_fifo_for_cpu_data_master_to_g110_core_burst_19_upstream_module:rdv_fifo_for_cpu_data_master_to_g110_core_burst_19_upstream" Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(340): used initial value expression for variable "arg_copy" because variable was never assigned a value Warning (10542): VHDL Variable Declaration warning at altera_europa_support_lib.vhd(344): used initial value expression for variable "arg_length" because variable was never assigned a value Info: Elaborating entity "g110_core_burst_19_downstream_arbitrator" for hierarchy "g110_core:inst|g110_core_burst_19_downstream_arbitrator:the_g110_core_burst_19_downstream" Warning: Using design file g110_core_burst_19.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project Info: Found design unit 1: g110_core_burst_19-europa Info: Found entity 1: g110_core_burst_19 Error (10511): VHDL Qualified Expression error at g110_core_burst_19.vhd(350): A_SRL type specified in Qualified Expression must match std_logic type that is implied for expression by context Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 193 warnings Error: Peak virtual memory: 313 megabytes Error: Processing ended: Wed Apr 28 15:33:10 2010 Error: Elapsed time: 00:00:24 Error: Total CPU time (on all processors): 00:00:20 Error: Quartus II Full Compilation was unsuccessful. 3 errors, 193 warnings   The hardware guy says it's an internal error so any idea how to get around this?   Paul

[Altera_Forum]

Is g110_core a custom IP in your design?

[Altera_Forum]

--- Quote Start ---  Is g110_core a custom IP in your design?  --- Quote End ---   g110_core is the project which does contain custom IP

[Altera_Forum]

If any of the custom IP includes an avalon slave with burst capabilities, there could be a type mismatch on one of the burst control signals. Having a look at the line 350 of g110_core_burst_19.vhd may help in finding the problem.