NiosII Debugging + Dual Port RAM Problems

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

NiosII Debugging + Dual Port RAM Problems

955 Views

Hello,

I have a system with one SOPC component that contains a Dual Port RAM, with one side conneted to Nios, by Avalon, as a MMSlave. The other side is accessed by the peripheral specific logic. I tested my system for simultaneous access on both sides. When I run it with Nios in debug, it only works (it means, the peripheral side can read/write correctly) when debug is in pause. When is is freely running, the access by the logic fails. On the Nios side, everything is ok.

Running the same system without debug, booting from EPCS, both sides work properly. Does anyone has already get the same situation? Any ideas are welcome. I´m using EP3C5F256

Thanks,

Lucas

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.