Programmable Devices

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

Programmable Devices

Discussions

MAX 3000a Ioh and Iol specifications

How does one overcome limitation of altera clock control block inputs?

All Pins list with tool Pin Planner

Issues with Max10 push button

reset sync design logic

Cyclone V deserializer maximum bitrate

Absolute maximum I/O/Analog pin input current

Enumeration of I/O banks with I/O type, voltage, pin function for 10AS016E4F29I3SG

EQFP pin spacing 0.4mm or 0.5mm?

Cyclone V SoC Migration to Arria 10 SoC

need to License for ARM hard processor

DE1-SoC HPS DDR3 Controller with UniPHY fitter error

MAX10 ADC sample store with threshold violation detection core

How to buy 1 or 2 Cyclone V GT FPGAs for protype board?

Unable to simulate the testbench in Modesim

Featured Content

Quartus Prime Design Software - JTAG usage

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage