Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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No qdrii ddr report

Altera_Forum
Geehrter Beitragender II
1.145Aufrufe

Hello, 

I am using stratix iv and quartus 10.1.  

my project compile without any error, but when I run DDR report in timequest timing analizer I have this error : 

 

warning: Ignored filter at uniphy_qdrii_report_timing_core.tcl(197) : my_inst........ could not be matched whit a keeper or register or port or pin or cell or net  

 

Missing required positional arguments: <body> 

--------------------------------------------------------------------------- 

Usage: foreach_in_collection [-h | -help] [-long_help] <variable_name>  

<collection> <body> 

-h | -help: Short help 

-long_help: Long help with examples and possible return values 

<variable_name>: Variable name 

<collection>: Collection 

<body>: Body 

--------------------------------------------------------------------------- 

I find in altea files that to solve this proble (the example speeks about DDR3) I must select auto leveling. I don't know how to select this in sopc builder I didn't find any thing refering to that. 

Please help !!!!
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2 Antworten
Altera_Forum
Geehrter Beitragender II
458Aufrufe

please help :)

Altera_Forum
Geehrter Beitragender II
458Aufrufe

no one is here ?? please help

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