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Hi,
I am trying to assign the DDR3 SDRAM pins to Bank 7A of ARRIA II GX FPGA. But the same is showing compilation errors "The I/O Standard is compatible with this bank " The I/O standard chosen is SSTL Class-I 1.5V and this is as per development board guidelines. Please Help..Link Copied
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The reason for the error message can be, that you have assigned I/O standards with a voltage different from1.5V to the same bank.
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No, I have assigned the same I/O standards with a voltage different of 1.5V to the same bank of 7A

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