Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19199 Discussions

Not correctly read silicon ID from the EPCS64.

Altera_Forum
Honored Contributor II
893 Views

Hi. 

For access with EPCS64 from Cyclone IV I use IP-core ALTASMI_PARALLEL. 

When I read silicon ID from the EPCS64, epcs_id[7..0] = 0x0B (0000.1011), but should be 0x16 (0001.0110). 

 

The clock frequency of ALTASMI_PARALLEL - 20 MHz. 

 

I brought on SignalTap epcs_id[7..0] and read_dout_reg[7..0] (the shift register of the ALTASMI_PARALLEL). 

After reading the silicon ID on Signal Tap epcs_id[7..0] = 0x0B, read_dout_reg[7..0] = 0x16. 

 

There is an assumption that the value on the bus epcs_id[7..0] is latched on the 1 cycle before. 

 

Has anyone such a problem?
0 Kudos
1 Reply
skat_for
Beginner
111 Views

Hi.

I work with EPCS1SI8.

When I read silicon ID from the EPCS1SI8 marking=Zb28x, epcs_id[7..0] = 0x04 (0000.0100), but should be 0x10 (0001.0000). 

When I read silicon ID from the EPCS1SI8 marking=9802X, epcs_id[7..0] = 0x19 (0001.1001), but should be 0x10 (0001.0000). 

Is the code identical,what is the reason?

Подаю команду command [7..0]= 0xF9 (1111.1001).

Code:

uint8_t data=0xF9;

PINS_HIGH(micra.DCLK);
PINS_LOW(micra.nCS); //green
//////////////////////////////////////////////////////////////////Write comand
for( uint8_t i = 0; i < 8; ++i)
{
PINS_LOW(micra.DCLK);

(data & 1 ) ? PINS_HIGH(micra.ASDI) : PINS_LOW(micra.ASDI);
data >>= 1;

PINS_HIGH(micra.DCLK);
delay_nop(1);
}

PINS_LOW(micra.DCLK);
PINS_HIGH(micra.ASDI);
//////////////////////////////////////////////////////////////////data - read
for(uint16_t i = 0; i < 8; ++i)
{
PINS_HIGH(micra.DCLK); //YELOU

a = READS_PIN(micra.DATA);
data_out|=(a << i);

PINS_LOW(micra.DCLK); //YELOU
delay_nop(1);
}
PINS_HIGH(micra.nCS); 
PINS_HIGH(micra.DCLK);

Reply