I have a Cyclone V design with the the V-Series Avalon-MM DMA for PCI Express (yeah, I know it's been obsoleted, tell my S/W colleagues that). I did the first build with QPS 17.1; there have been other issues, which I have worked around. But now I see failures in simulation of Read DMA operations (from system memory to local memory); the failures include both corrupted address and weird Avalon-MM protocol behavior, both from the local memory avalon master interface from the PCIe/DMA core.
I tried again, using QPS 19.1. In this case, the design would not load into the simulator, due to missing modules.
Is this macro a dead end? Thanks.
Failure details are in the attachment.
Environment: Windows 10, ModelSim DE64 V. 10.7a
The Cyclone V PCIe AVMM DMA IP is not available in v19.1std, so you might not able to run the simulation in v19.1std
I'm using the example design (pcie_de_ep_dma_g2x4_cv.qsys) in the link below to generate the simulation testbench in v18.0std (v17.1std is not installed here), and it is passing the simulation.
Perhaps we can start the debug with this example design to determine if the same problem can also be observed before jump into the detail of your design.
If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.