OCT serial termination of Cyclone IV devices

[Alex6401]

Hi community,

please, have a look at attached dokument "Cyclone_IV_OCT.pdf

Table 6-2 Part 1 depicts different Rs OCT values in Ohms for several different I/O standards, single ended as well as differential. Looking at Part 2 of the same table (6-2) in general and at LVDS I/O standard specific there is no Rs OCT values specified. Does this mean that differential LVDS mode does not have any support to OCT Rs (serial) termination? Is the serial termination only valid and relevant when using single ended transmission lines? Should not this be a fact both for single ended and differential lines?

Seral termination could be very important to reduce impedance missmatches in transmission lines.

Too fast edges of clock and data lines in combination with poor pcb layout could create unwanted overshoots and ringing. In my case I suspect this is a the root problem of my EMI problems.

Any out there that have any experiance of this kind of issue? Is there some way to setup the Quartus assignment editor  to accept OCT Rs termination to my differential LVDS (2.5V) lines?

Best regards

Alex

[FvM]

Hi,
true LVDS standard is defined by a nominal output current of 3.5 mA. This results in a driver impedance of 300 to 400 ohm. This is in accordance to LVDS standard that doesn't require a specific source side termination impedance.

If you want 100 ohm (2 x 50 ohm) series termination together with LVDS output level for some reason, you can use emulated LVDS (LVDS_E3R) IO-standard that allows to adjust level and output impedance independently at the cost of three external resistors per LVDS pair.

Regards

Frank

[Alex6401]

Hi community,

please, have a look at my attached dokument.

So my question is:

Would it be possible to some how use the FPGA OCT feature or something else in the assignment editor in Quartus to achieve this thing inside the FPGA or must i change the pcb layout and put in 10 external resistors?

Best regards

Kenneth

[FvM]

Hi,
your previous post asked about OCT Rs termination which isn't used or required for LVDS. Now you are referring to receiver Rd termination. Unfortunately it's not provided by Cyclone IV or Cyclone 10 LP FPGA series. LVDS receivers on Cyclone IV need external 100 differential termination. For a complete assessment, which device is driving LVDS, how long is the connection?

[Alex6401]

Hi,

I described that in my attached file "Standard LVDS.pdf".

The device driving LVDS (LVDS Tx) is a Dual Link LVDS Tx implemented in a Cyclone IV E FPGA. The receiver end (LVDS Rx) is a TFT display.

The TFT display is terminated by 100 Ohm per differential pair.

The total transmission line between FPGA and display consist of pcb traces from the FPGA to a LVDS connector and from the LVDS connector there is a twisted pair LVDS cable connected between the FPGA board connector and the display connector. The length of this transmission lines is about 25 cm and the speed of data is 520Mbps, so this transmission line must for sure be impedance balanced.

This should be done by making single ended pcb traces impedance ~50 Ohm and differential impedance ~100 Ohm between each pair.

When I analyzed the FPGA pcb board  layout regarding routing the LVDS connections I found it to be a poor layout. LVDS pairs changing layers several times and at different places giving unnecessarily amount of  via:s etc.

All in all I think this poor layout, with so much impedance discontinuity, is the main root problem to the excessive EMI problem I have.

My intention in this issue was to slow down the clock and data signals rise and fall time in the FPGA a litle bit to see if that can reduce the emission enough to make EMC accordance.

So my question really was if I could set a OCT serial resistor value in the Cyclone IV E FPGA using the Quartus assignment editor or if I must put this resistors in the FPGA pcb layout?

I hope I'm totaly correct intepreted now.

Best regards

Kenneth

[FvM]

Hi,
as stated multiple times, LVDS transmitter does not use termination resistors. You can refer to the diagram that you posted above (Standard LVDS.pdf). Differential termination is placed at the receiver side, as you clarified now, the receiver is a TFT display that is equipped with required termination resistors.

LVDS IO standard is the option with lowest level and respectively lowest EMI potential, presuming you are using true LVDS rather than LVDS_E_3R IO standard.

You can optionally further reduce LVDS level by adding an external differential termination resistor at the transmitter side, there's however a risk that required RX level isn't achieved. LVDS standard doesn't require transmitter side termination. I won't expect termination to reduce signal slew-rates. 

Regards
Frank

[Alex6401]

Hi,

it's not a termination (parallell) resistor I'm speaking about,  it is a serial resistor and a serial resistor for shore does have impact on signal slew-rates.

Of cause you can't slow down the edges too much, one must still satisfy set up and hold demands.

Earlier in this thread I posted the document Cyclone_IV_OCT.pdf

That document shows that you, for several different logig levels, can choose some small (<100 Ohm) different Rs, serial Resistor values.

If this was a parallell single ended interface, for instance an external memory interface with address, databus and control signals you could slow down the rise and fall time on this signals, if the pcb layout is poor, using the Rs feature and that MIGHT help you to reduce the  emission from the pcb enough, instead of a layout change.

This is clearly not the case for differential lines regardless type of LVDS.

That is quite pity I think and I can not really understand why?

In my world a differential pair consist of two single ended traces and they are each other's inverse. So why could you not use Rs resistors in this case?

Best regards

Kenneth

[FvM]

Hi,
Rs OCT is implemented in Altera FPGA by selecting output transistors of different drive strength. LVDS IO standard is already using a specific drive strength selection (the lowest available), there's no option to further decrease it. 

Drive strength of LVDS output correponds to 200 - 300 ohm Rs, adding e.g. 50 ohm would achieve little except for slightly reducing output current. To reduce slewrate, you can try small parallel capacitance of a few pF, either between differential lines or each line to ground. As 520 MBPS isn't much below maximal 700 MBPS LVDS rate, there is probably not much margin to slow down the signal without affecting reliability.

I appended Cyclone IV LVDS output characteristic (min, typ, max), extracted from IBIS file. I added a 220 ohm resistor curve for comparison.

Regards
Frank 

[Alex6401]

Hi,

okay Frank, Thank's! You can close this thread now.

Best regards

Kenneth

[AqidAyman_Intel]

Thank you, Frank, for your answers. I’m glad that the question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.