Odd behavior when Master reads from two different data width memories!

[Altera_Forum]

Hi, 

 I have an Avalon master with 256 bit data bus width which is interfaced to two slave memory components: 1. Memory 1 - 256 bit data bus width Avalon slave  2. Memory 2 - 32 bit data bus width Avalon slave - Look up table (initialized to mem(A) = A)  For the first component, all read / writes are correct  For the look up table (LUT), the designated addresses coming out and seen on the avm0_address are correct, location = low byte / 4  avm0_address: 0x040400CC , 0x040403D4, 0x0404006E4, 0x040409EC ..... (Correct) location (hex) : 33, F5, 1B9, 27B ..... (Correct)  problem1: The address seen entering the LUT is wrong :confused: LUT addr (hex): 32, F6, 1BF, 278 ..... (Random but close) problem2 Since the LUT is initialized such that each location has the a data equal to its corresponding address, the data read from memory is equal to above!  yet the data on the avm0_read master is doesn't also match: avm0_address(hex): 700, 700, 700, 700, 278  Hope you can help.  Thanks

[Altera_Forum]

refer to the avalon specification of the masters and slaves of different bus sizes, I guess u could find useful articles there. since the data bus width of ur master is bigger than the slave, it probably does read or write actions on consequtive addresses for a signle read/write istruction . This part of the avalon protocol is quite confusing!!I once had similar problems.

[Altera_Forum]

Well I did, and I do quite understand it very well .. but the problem here is why once the correct address is issued on avm0_address .. it slightly changes once it reaches the slave, observe that the same address reaches the slave but with +/- some value .. that's the address is close but not exact .. that's what confuses me :eek: