Question about tco and th in CycloneII

[Altera_Forum]

Hello，everyone！I have a question about Register's Tco and Th in CycloneII device. Now see my picture below.  

'Clk_sys' is system clock ,120Mhz . 'Clk_sys' is devided by PLL ,and generates 2 clocks, 40Mhz and 30Mhz. Now I use the 30Mhz clock sampling the data from 'Reg2'. Here I have a question,look the next picture. http://pic.yupoo.com/dongshusong/B8ye660f/UOooQ.jpg  The 'tco' is Reg2's Tco. And I found in Cyclone II device ,Tco = 0.304ns, Th = 0.306ns. So at the time marked by red arrow, when Reg1 samples the data , the data's Th is 0.304ns, doesn't enough to Reg1（0.306ns）. Does metastability will happen ? Thanks for your help! http://pic.yupoo.com/dongshusong/B8ygHmuS/qX0mk.jpg

[Altera_Forum]

Your post is clear but abstract. If I assume your figures then: 

 As you noticed, the worst case is when clocks are in phase (cycle1 or the cycle at red arrow). In this case the worry should be about tH violation at reg1 rather than tSU. Since tCO of reg1 (is stated as .304ns) and tH as .306ns then violation is expected i.e you have .002ns of tH window violation.  However, you need to realise that tSU/tH/tCO is usually quoted at pins and is not same as actual internal register tSU/tH (also called micro). Altera does not usually give figures for these as the internal figures are left for timequest to check (not the user). The pin figures on the other hand are not fixed but programmable by user through delays. You also need to realise clock/data delays may vary the relationship.  So if it is me I will run timing and see, if it fails I will do some bridging beteen clocks e.g. a small fifo or phase changes or edge choice.

[Altera_Forum]

data delay may change the relationship , thank you, kaz!!