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One Sample Delay Code

Altera_Forum
Honored Contributor II
‎10-19-2009 08:06 AM
1,047 Views

I have a 13 bit bus singal with a reference clock, each 13-bit represents a sample sychronized with the rising edge of the reference clock,any idea (vhdl code) on how i can achive 1 sample delay?

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Altera_Forum
Honored Contributor II
‎10-19-2009 11:29 AM
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By inserting a D Flip-Flop (for each bit), with your sample in input and your clock in clock input.

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