One or more serdesses, that's the question

[Altera_Forum]

I'm building a system with 4 transmit channels, all carrying the same data. What would be the pros and cons of using one serdes and split the output to 4 channels (data and clock) or using a separate serdes for each channel, fed with the same input data? 

 Right now I'm using the one serdes solution with internal PLL, which uses less resources, but I'm facing stability problems. Don't know the reason for that, yet.  Target device = EP4SGX230

[Altera_Forum]

What type of data and what's the data rate? How much distance are you running the data and over what medium? I assume you are using a fanout buffer of some kind to split the data. 

 Jake

[Altera_Forum]

Hi Jake, 

 The data is 8 bits LVDS, only 50 MHz. Not a standard protocol. I'm using HSMA-tx and HSMB-tx with corresponding clocks of the Stratix IV development kit. Distance is about 20 cm (8") of matched impedance PCB track.  No, I don't use fanout buffers. I direct go from serdes to (multiple) output pins. What would be the benefit to use a buffer in this case? The functionality doesn't change. And if the load is too high for the serdes, why doesn't Quartus insert the buffers automaticly?   Do you know if there's Altera literature on the use of buffers? Which one would you use? alt_outbuf_diff? Isn't that one used automaticly when I use LVDS outputs? I'll check the netlist.  Alot of additional questions. Thanks for your respons.  Ton