is it possible internal signal to be in process sensitiv list (vhdl)

Altera_Forum · ‎05-13-2010

hello

i am using ciclone 2. i do vhdl module and i want to ask is it possible itnernal signal to be part of sensitive list of process:


process   (clock, second, ten_7segment_sign_vector ,  q_2_HOURS_vect_signal, ten_hours_signal_vector , two_hours_vect_signal ) 
  begin
--if ((ten_7segment_sign_vector = "0100") and (q_2_HOURS_vect_signal = "1001") and (hours_10_signal_vect = "0011" ) and (hours_2_signal_vect = "0010") ) then 
--if ((ten_7segment_sign_vector = "1001") and (q_2_HOURS_vect_signal = "0101")) then 
if (second'event and second = '0') then
if ((ten_7segment_sign_vector = "1001") and (q_2_HOURS_vect_signal = "0101")) then 
  if ( (ten_hours_signal_vector = "0011") and (two_hours_vect_signal = "0010") ) then 
 -- rst2_signal <= '1'; 
--resert10hours <= '1';
rst10_signal <= '1'; 
--rst10hours <= '1';
reset_10_hours <= '1' ;
reset_2_hour <= '1'; 
reset_2_hours <= '1';
else 
  reset_2_hours <= '0';
  reset_10_hours <= '0' ;
  rst10_signal <= '1';
  reset_2_hour <= '1';
  end if;   
else 
  reset_10_hours <= '0';
 -- rst2_signal <= '0'; 
  --resert10hours <= '0';
rst10_signal <= '0';
--rst10hours <= '0';
reset_2_hour <= '0'; 
reset_2_hours  <= '0';
end if ;
end if ; 
  end process;

where second is internal signal used as clock

Altera_Forum · ‎05-14-2010

Yes, but what you are doing is very bad. Use the clock as a clock ONLY. dont make your own clocks unless they are the output of a PLL.

Generate enable signals instead.