Optimizing a design

[Altera_Forum]

Hello every body; 

I have a function that makes a transformation on th input byte, to produce an output byte, I used a look up table methode to realize this function, then I tried to realize it usung a carnaugh map. the utilization of the second methode is as 3 times larger than using the lut methode and i use stratix 3 fpga. my question is, is it true that using the lut methode takes less resources than using the optimization using carnaugh map?? thanks.

[Altera_Forum]

how big is the lut? 

The LUT uses a simple ram, so is nice and compact. I dont know what the transform is, so I assume it would require plenty of logic?  Why not post the code?

[Altera_Forum]

the transform is simply the SubBytes transform used in the AES cipher system, is it true that the fpga nature is suitable for implementing a design using lut so it take less resources, and if I made ASIC design the carnaugh map optimization would take less resources than lut. 

Thanks

[Altera_Forum]

--- Quote Start ---  the transform is simply the SubBytes transform used in the AES cipher system, is it true that the fpga nature is suitable for implementing a design using lut so it take less resources, and if I made ASIC design the carnaugh map optimization would take less resources than lut. Thanks  --- Quote End ---    In ASICs you can design your own logic at gate level.  FPGA fabric does not have user gates. Instead it provides luts (and flips) to realise logic.  your input to truth table is input to lut and the lut output is the truth table of your logic. It is equivalent in functionality. Carnaugh mapping is not needed for fpga as the tool optimises the code. In ASICs I assume tools can do that as well. Boolean algebra and carnaugh are traditional manual methods. Why wouldn't modern tools not be able to do that instead? Just like you don't need to get sine(x) for x = 1: n using pen and paper, you use a tool.

[Altera_Forum]

Thanks Mr kaz for your attension; 

your reply add to something I miss, but I want to know if these analysis tools are more effecent to analysis and optimize my code than a Manuel analysis, I know it is very hard to make this manual optimization but I mean to optimize the fundamental operations in my project that is repeated many times and affect my project resources directly.

[Altera_Forum]

--- Quote Start ---  Thanks Mr kaz for your attension; your reply add to something I miss, but I want to know if these analysis tools are more effecent to analysis and optimize my code than a Manuel analysis, I know it is very hard to make this manual optimization but I mean to optimize the fundamental operations in my project that is repeated many times and affect my project resources directly.  --- Quote End ---    Tools can do a lot of work but expert manual coding can beat them sometimes. There are various documents on coding styles. I can state the following as an example:  you have 100 filter coefficients: if you just declare them as wires (constants) that will only take routing resource. If you decide to zero them during reset then apply registered assignment then you will waste 100 registers.  If you have several filter modules using same set of coefficients then you better declare one set of wires central to all modules rather than per module to lower routing cost.  The tool will not go far enough to remove registers because that is what you asked for.