Output Linux´s Video to VGA controller in FPGA Fabric through AXI on CV SoC

[Altera_Forum]

Hi all,  

 I designed a custom expansion board for the de0 nano SoC with an AD 7123 video DAC and a wolfson audio dac.  I have an VGA controller running fine on the FPGA fabric side (driving the AD7123) but now i need to output the video from linux to the VGA controller (Angstrom´s X-Windows).  I have high level on c programming but i´m not an expert in Linux Kernel Driver development.  Somebody can help me ?  I know it´s not very easy to do ...  Thanks in advance.

[Altera_Forum]

Hi, 

 I had a similar task but with creating a soundcard driver: http://stackoverflow.com/questions/34575899/creating-a-simple-audio-driver-for-a-cyclone-v-soc-linux The dummy driver (snd-dummy) proved to be very useful for such a task, maybe you should have a look in the kernel sources for something similar on the video side.  Some links which I found in a quick search: linux framebuffer documentation (somewhat dated) (https://www.kernel.org/doc/documentation/fb/framebuffer.txt) discussion on phoronix (http://www.phoronix.com/forums/forum/linux-graphics-x-org-drivers/x-org-drm/41971-how-to-make-framebuffer-look-like-a-real-monitor) xf86-video-dummy (http://cgit.freedesktop.org/xorg/driver/xf86-video-dummy)  I don't know if anything of this really is "state-of-the-art", or if there is some other way to do it in current systems/kernels, though.  Good luck!  Regards, Philipp

[Altera_Forum]

Hi, DE0 SOC has no RAM on fpga fabric, I read you write VGA is running fine, is taking image from memory or from pattern generator? 

Supposed all is fine are you able to fill in memory of VGA to display a pattern like lines and or color bar?  If hardware is really ok then you need to prepare a cross development gcc chain to compile code on PC Host.  This scenario you write, compile, transfer and debug code on target acting as an emulator.  If Linux is running on FPGA enough space is available, map a network drive on FPGA linux so you can also launch XWindows from terminal and display on workstation, then all development can be done on ARM setting all library and environment on.  Choose your way and prepare compilers and library too then it is just question of software.  http://www.ibm.com/developerworks/library/l-arm-toolchain/  http://gnuarmeclipse.github.io/toolchain/install/   Are you confident on how to write device driver and Unix/Linux signalling?  Regards

[Altera_Forum]

Thank you Phillip ! 

I will try with audio first. I know how to develop little loadable kernel modules but nothing more ...  In Rocketboards there is a linux distro modified for doing this with the sockit:  http://rocketboards.org/foswiki/view/projects/sockitlinarolinuxdesktop  " The video pipeline is implemented in the FPGA portion of the SoC using Altera's Video IP (VIP) suite. A frame buffer DMA component in the FPGA reads the video buffer information from DDR in the HPS and writes it into the video pipeline. A custom frame buffer driver was added to the kernel to support this."

[Altera_Forum]

I found this in rocketboards  

http://rocketboards.org/foswiki/view/projects/sockitlinarolinuxdesktop  This project utilizes Arrow SoCKit to demonstrate the LXDE X11 interface running on the Altera Cyclone V SoC device. This project allows you to boot linux with the penguin on a desktop display and run X windows. This project can be built using the features of the 13.0 release.

[Altera_Forum]

The de0 nanoSoC does not have sram on fabric side but i can make a expansion breakout , adapted to the nano headers  

http://www.play-zone.ch/en/waveshare-is62wv51216bll-sram-board.html or purchase a sockit.  But my goal it´s learn to do it for my own ...  Yes, i can output 1600 x 600 and i know hou to do litttle loadable kernel modules but this is more difficult

[Altera_Forum]

This project utilizes Arrow SoCKit to demonstrate the LXDE X11 interface running on the Altera Cyclone V SoC device. This project allows you to boot linux with the penguin on a desktop display and run X windows. This project can be built using the features of the 13.0 release.  

 http://rocketboards.org/foswiki/view/projects/sockitlinarolinuxdesktop

[Altera_Forum]

Hi nachodizz990, 

 thanks for the link to http://rocketboards.org/foswiki/view/projects/sockitlinarolinuxdesktop This could prove to be very useful for me as well, as I'm planning to do some video output in the future, though I'll try to use the MGTs for HDMI output. If it works at least, not sure about that yet...  Bye, Philipp

[Altera_Forum]

--- Quote Start ---  The de0 nanoSoC does not have sram on fabric side but i can make a expansion breakout , adapted to the nano headers  http://www.play-zone.ch/en/waveshare-is62wv51216bll-sram-board.html or purchase a sockit.  But my goal it´s learn to do it for my own ...  Yes, i can output 1600 x 600 and i know hou to do litttle loadable kernel modules but this is more difficult  --- Quote End ---    Hi, good job, learning is forever more better than reusing without understanding.  Thank for link to prebuilt modules, I take an eye to what can save time, anyway in your project cannot be of help, that is an SRAM and is too slow for video access, an SDram DDR is better and cost much less than static.  I see you pointed to rocket board example, that help a lot building compilers chain but also has prebuilt drivers, what happen if you load that image on your board? I suppose you need adapt fabric and all I/O on QSYS to match DE Nano hardware too.  Tomorrow if I get some spare time I check on resources of arrow board compared to DE0 nano soc  What you can see on VGA screen? If you booted system, are you able to allocate a video buffer in the user memory then initialise DMA registers to display it?  Regards

[Altera_Forum]

--- Quote Start ---  Hi, good job, learning is forever more better than reusing without understanding.  Thank for link to prebuilt modules, I take an eye to what can save time, anyway in your project cannot be of help, that is an SRAM and is too slow for video access, an SDram DDR is better and cost much less than static.  I see you pointed to rocket board example, that help a lot building compilers chain but also has prebuilt drivers, what happen if you load that image on your board? I suppose you need adapt fabric and all I/O on QSYS to match DE Nano hardware too.  Tomorrow if I get some spare time I check on resources of arrow board compared to DE0 nano soc  What you can see on VGA screen? If you booted system, are you able to allocate a video buffer in the user memory then initialise DMA registers to display it?  Regards  --- Quote End ---    The arrow haves ddr3 mem in both hps and fpga fabric sides, i think that surely the video block uses the fpga ddr3 memory. These example is useful to explore the kernel files and see how it works !!  I designed a expansion board (or cape) that fits perfectly with the nano soc, it includes an adv7123 video dac a wolfson audio codec but i will redesign it for adding a little ddr too(for the fpga side)

[Altera_Forum]

--- Quote Start ---  The arrow haves ddr3 mem in both hps and fpga fabric sides, i think that surely the video block uses the fpga ddr3 memory. These example is useful to explore the kernel files and see how it works !!  I designed a expansion board (or cape) that fits perfectly with the nano soc, it includes an adv7123 video dac a wolfson audio codec but i will redesign it for adding a little ddr too(for the fpga side)  --- Quote End ---    Hi, it is not really necessary at normal resolution, if you wish have full HD or 4HD then a separate memory is better due memory channel bandwidth reduce processor speed too.  Memory of HPS can be accessed from FPGA and FPGA memory controller can be accessed from HPS too.  Which IP did you used for your design and how are they interconnected on QSYS?

[Altera_Forum]

--- Quote Start ---  Hi, it is not really necessary at normal resolution, if you wish have full HD or 4HD then a separate memory is better due memory channel bandwidth reduce processor speed too.  Memory of HPS can be accessed from FPGA and FPGA memory controller can be accessed from HPS too.  Which IP did you used for your design and how are they interconnected on QSYS?  --- Quote End ---    I wrote the code by hand ! Its not connected to qsys, i have two versions, fifo and axi but now it runs freely without bus connection.  I placed a post in the general topics for asking forum members to a group purchase of mi next evaluation board you can see a picture of the board  I designed a verilog axi slave for acces the adc from linux, it runs fine and you can full configure it, i can pass you the code if you want

[Altera_Forum]

--- Quote Start ---  I wrote the code by hand ! Its not connected to qsys, i have two versions, fifo and axi but now it runs freely without bus connection.  I placed a post in the general topics for asking forum members to a group purchase of mi next evaluation board you can see a picture of the board  I designed a verilog axi slave for acces the adc from linux, it runs fine and you can full configure it, i can pass you the code if you want  --- Quote End ---    Good Idea, just check if this don't infringe forum rules, I am quite new and we need read FAQ or ask moderator, also ask Terasic for, Maybe I got interested to use DE0 Nano instead of DE1_SOC, just a question, why VGA when all new monitor are switching to HDMI?   About code, I can take an eye and try port to QSYS to share if you wish, this can improve the usability of your "cape". (Cape is the add on of Beagle Bone as for shield of arduc and boosterpak of TI, nothing to do with Terasic simply call "Daughter card")  After a long time coding by hand I decided to learn how QSYS work and now a lot of my module are near ported to. It is a valuable tool and save a lot of time on connecting layer.  Some drawback are still on, Linux version is plagued by a bug on graphical and sometimes PLL IP must be edited by hand, this is not a problem, as for Linux when GUI doesn't work or don't know how to I just edit config files script or just do some command line actions.  IMHO switch layer from processor and peripheral can be optimized to reduce silicon usage, but it work and for now things fit on selected size with some small margin.  PS: remember to use time compensated design on PCB artwork.

[Altera_Forum]

`define DZERO_GREATER 2 

`define ADC_CONVST_CYCLES ( 10 - `DZERO_GREATER ) `define WAIT_CYCLES 5 `define TRANSFER_CLOCKS (12) `define SCK_ON ( `ADC_CONVST_CYCLES + `WAIT_CYCLES ) `define SCK_OFF ( `SCK_ON + `TRANSFER_CLOCKS ) `define SHIFT_OFF (`SCK_ON + 6 )  module ltc2308 (   clk,go,ADC_SDO,chansel,  ADC_CONVST,ADC_SCK,ADC_SDI,done,data   );  input clk,go,ADC_SDO; input [3:0] chansel; output ADC_CONVST,ADC_SCK,done; output reg ADC_SDI; output reg[11:0] data;  //////////////////////////////////////////////////////////////////////// //Generates negative reset_p pulse signal at go signal posedge. //////////////////////////////////////////////////////////////////////// wire resetp; reg rstbegin; assign resetp = ( (rstbegin == 1'b0) && (go == 1'b1) )? 1'b0 : 1'b1;  always@(posedge clk) begin  rstbegin <= go;  end  //////////////////////////////////////////////////////////////////////// //CFG bits at resetp //////////////////////////////////////////////////////////////////////// reg [5:0] cmd; always@(negedge resetp) begin   cmd <= { chansel, 2'b10};   end //////////////////////////////////////////////////////////////////////// //Cycle counter //////////////////////////////////////////////////////////////////////// reg [7:0] counter; assign ADC_CONVST = (counter>`ADC_CONVST_CYCLES)? 1'b0 : 1'b1; always@(posedge clk or negedge resetp) begin  if(resetp==1'b0)  counter <= 8'b0;  else if(done == 1'b0)  counter <= counter + 1'b1; end //////////////////////////////////////////////////////////////////////// //SCK //////////////////////////////////////////////////////////////////////// reg sckon; assign ADC_SCK = (sckon==1'b1)? clk : 1'b0;  always@(negedge clk or negedge resetp) begin  if(resetp==1'b0)  sckon <= 1'b0;  else if ( (counter>=`SCK_ON && counter<`SCK_OFF) )  sckon <= 1'b1;  else  sckon <= 1'b0; end //////////////////////////////////////////////////////////////////////// //RX //////////////////////////////////////////////////////////////////////// reg [3:0] irx; assign done = (irx > (`TRANSFER_CLOCKS - 1) )? 1'b1 : 1'b0;  always@(negedge clk or negedge resetp) begin  if(resetp==1'b0) begin   data <= 12'b0;  irx <= 4'b0;  end   else if ( sckon == 1'b1 ) begin  irx <= irx + 1'b1;  data[11-irx] <= ADC_SDO;  end end //////////////////////////////////////////////////////////////////////// //TX //////////////////////////////////////////////////////////////////////// reg [2:0] itx; always@(negedge clk or negedge resetp) begin  if(resetp==1'b0) begin  itx <= 3'b0;  ADC_SDI <= 1'b0;   end  else if ( (counter >= `SCK_ON) && (counter < `SHIFT_OFF) ) begin  itx <= itx + 1'b1;  ADC_SDI <= cmd[5-itx]; end  else   ADC_SDI <= 1'b0;  end  endmodule   what means "time compensated design" ?  I use vga because it´s easy to find a cheap "second hand" monitor for use with fpga and almost all people haves one vga monitor ...  But i will add hdmi too !!  I like qsys so much i enjoy a lot designing my own system i love this architecture, now i have a nios on the fpga side and the system its similar to the I.MX6 soloX with the cortexA + cortex M but with a lot of flexibility, i´m designing a board with the cheaper cyclone V soc i found at mouser 5CSEBA2U19C86N [h=1][/h]

[Altera_Forum]

Hi nachodizz990, Hmmm i am not so proficient in Verilog due I am prevalent VHDL developer but at glance this code seems an ADC module interface than video... 

  About high speed design you need compensate for both impedance and time of fly, all signal must arrive at same time to DDR Chip.  try these if you like video or recommendation about DDR wiring:  in first this is related to RF and High speed, DDR are High speed and if lines impedance is not adapted they become RF transmitters too.  https://www.youtube.com/watch?v=6jrvzu7eqiw   This is a lesson on how to route an High Speed LVDS track.  https://www.youtube.com/watch?v=blhlmq2ho1w  https://www.youtube.com/watch?v=41r3kkm_fme  your tools resemble Altium so check also this on length compensation  https://www.youtube.com/watch?v=bzrdfcjilga     If you like readable document or a book I can post reference.  Regards

[Altera_Forum]

Yes, i know , lenght matching! 

 I know Robert Feranec and Fedevel, i´ve seen all their videos some time ago...

[Altera_Forum]

--- Quote Start ---  Yes, i know , lenght matching!  I know Robert Feranec and Fedevel, i´ve seen all their videos some time ago...  --- Quote End ---    I seen few minutes before to post and I like them, I am more incline to document but sometimes I also watch some lesson. The Analog Device too is a good tutorial on how plane work and RF, take an Eye.  About DDR on daughter board I fear there where not enough pin, some need to be free for user interaction, a better solution, as I asked ,was just to use HDMI:  it can consume just 4 LVDS pair and one PLL, you can deserialise HDMI with a chip, fed VGADAC then analog monitor, if you do that on a short adapteur signal integrity can be better.  Anyway this has sense on old analog CRT monitor, if you own an LCD analog input is first converted to digital then fed serially to LCD panel on parallel or HDMI Like Lvds serial port.

[Altera_Forum]

Thanks , i´m planing to remove the 7 seg and add one joystick and some pushbuttons (like gamepad) and leds...  

The 7 seg fills a lot of space and it´s not so usefull... I will place a ddr1 or sram (x16 only) mem because the header connection its dangerous for ddr3. In addition the pcb tracks from the soc to the headers have unknow lenght and impedance because they are not designed to be a memory bus, so i need to use sram or ddr1 as much ... I will make two versions, one for the nano soc with ddr and other for the nano without ddr because it includes onboard ddr. Furthermore if i only make one board this will not feet perfect with both nanos  I have enought idle pins the other header is fully empty   What is your opinion?  Your idea is to transmit hdmi from fpga to ad 9980 and then feed the 7123 wit the 9980´s output? The main concern it´s that both chips are expensive ...  And what about use only the 7123 and people who has not vga monitor use an vga to hdmi adapter? Or dont use any ad chip and feed the hdmi directly from fpga and place and vga conector too but with 5 bits r-ladder dac  If we have fpga why use an 9980 like chip, we can make it in hdl ...  Send me your mail for discuss the layout if you like...

[Altera_Forum]

--- Quote Start ---  Thanks ,  i´m planing to remove the 7 seg and add one joystick and some pushbuttons (like gamepad) and leds...  The 7 seg fills a lot of space and it´s not so usefull... ........... I have enought idle pins the other header is fully empty   What is your opinion? ....   --- Quote End ---     No problem send you my email, I prefer remain here so other can contribute to development and or wish list.   My idea can be to make some piggy back so one can add what it like, one board for memory has length and time constraint too so just the memory on board then plug other interfaces to top that can bbe everything.    Ex LCD TFT + Key + Joy   16x2 LCD + key + joy   ADC DAC   Motor Interface..  Just what you think can be added on a stack as it is on Beagle Board (Black-)     --- Quote Start ---   Your idea is to transmit hdmi from fpga to ad 9980 and then feed the 7123 wit the 9980´s output? The main concern it´s that both chips are expensive ...  And what about use only the 7123 and people who has not vga monitor use an vga to hdmi adapter? Or dont use any ad chip and feed the hdmi directly from fpga and place and vga conector too but with 5 bits r-ladder dac  If we have fpga why use an 9980 like chip, we can make it in hdl ...  Send me your mail for discuss the layout if you like...  --- Quote End ---     My idea was to leave board with HDMI using few pin pairs, impedance is not correct but can be close and a very short stub refelect also a small amount of energy.   On the other side of HDMI you can build an universal HDMI 2 VGA and it can be used for every monitor. You can provide also an LCD TFT standard 40 pin connector to use for parallel TFT.  We can develop just using a small MAX V.  See you, my time slot now is terminated see you soon.  Roberto