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Hard to say. you better give more details about your design from NCO to DAC to the way you see amplitude. Do you use any fft?
You can exclude NCO by looking at max/min mif values per each sweep point.I am sorry I can't run any projects at the time being.
I suggest the easiest way is to use nios or signaltap(or simulation) after adding this simple piece of code on your sine data:
-- get max data
process(clear,clk)
begin
if clear = '1' then
temp <= (others => '0');
elsif rising_edge(clk) then
if temp < data then
temp <= data;
end if;
end if;
end process; you can use nios to clear temp or read its value per each frequency. Remember to make temp and data signed type
I have already inverted sign bit and is outputing a wave fine. The issue is when frequency sweeping the amplitude is changing.
Is there any files for the frequency response of the DAC? I mention the ADC as I guess it will have a similar issue when feeding a signal back into the card.DACs do not have frequency response per se. It just converts digits to a ladder of values.
If you inject any data into DAC, it should be converted to the ladder of corresponding digits. There is no way the DAC will discriminate against the frequencies. Assuming you are not violating the DAC sampling speed. Make sure your sine data are at DAC's sampling frequency and that you are not violating the sampling rule. I don't think you are violating because you generate them in the digits(not from ADC) so make sure your DACs sampling frequncy is same as that of your sine data.Hold on...It could be you are having sinc effect of DAC's hold device.
DACs normally have inverse sinc filter to compensate for that. But it could be you are right, as you get closer to Fs the amplitude will droop and becomes zero at Fs(in theory). So there is no problem now. Basically I missed the fact that your DAC is basic without inverse sinc correction.I have checked the clocks and can confirm that it is the same clock for both of them.
I am trying to find out more about the ADT1-1WT componet that is on the board. As i know I cannot produce Freq of under 1Mhz as this is acting as a high pass filter - which I can live with. But I think it is definately doing something to my amplitude as I change frequency in the range 10Mhz to 45Mhz.I will assume now your DAC has no sinc correction. You will get amplitude droop(due to hold device similar to low pass average filter for the duration of one sample). This droop goes towards zero at Fs and its multiples(after successive lobes). The remedy is to add inverse since filter somewhere e.g. in the fpga or in the dac(some dac have it) or in the analogue domain.
There should be no problem with lower frequencies as they are passed bestI have to say the output does look rather like a sinc function :P I am using the DAC / ADC on the stratix II card.
What is a inverse sinc filter and have they got a megacore for it? Also is there a link that explains the thoery of this effect. Thanks alot forr your help.sinc distortion is caused by the hold effect of DAC(it doesn't affect the DAC value conversion itself, i.e. the ladder of values will always follow the conversion rules) but the hold effect is very much like any averaging low pass filter(analogue-wise).
The amplitude droop equation is this: a = A * sine(x)/x where x = pi * f/Fs, A is amplitude at f without distortion the inverse to be applied is x/sine(x). This is the frequency response required from the correction filter. You then apply ifft in Matlab to get coefficients. Another remedy is to upsample so high that your signal is always far away from main shoulder of distortion. make a search for inverse sinc and there is alot around.The NCO IP has a frequency independent amplitude. Have you an idea, how it should perform different? I don't.
If you're referring to a particular hardware platform, e.g. a development board, it would be a good idea to mention the board and the frequency range of your test, too. If it's e.g. a DSP board or a Terasic ADDA board, the have a transformer coupled output with an about 400 kHz to 1 MHz lower edge, it can be easily seen from schematic (and even by looking at the board, if you miss the schematic).here is a matlab example of coefficients for inverse sinc
%inverse sinc filter(31 taps)
n = 31;
f = linspace(-.5,.5,1024);
A = 1./sinc(f);
h = fftshift(ifft(fftshift(A)));
h = h(513-15:513+15); %truncate
h = h/sum(h); %normalise
in many cases your interest is in the passband and can improve on it at the expense of stopband
I previously missed some of the contributions in the thread, so my first post was somewhat behind the discussion. If you have e.g. 100 MHz DAC clock, the sinx/x effect is rather strong of course, and everything should be clear now. If you use the SLP-50 antialias filter, there's an additional 1 dB amplitude drop at 47 MHz.
So this must be a common problem when using the DAC on the S180 then?
I am surprised that it doesn't have this feature in the DAC like you mentioned some other ones do to counter act the sinc droop? Also found this about the theory if anyone else is interested. http://www.maxim-ic.com/appnotes.cfm/an_pk/3853The basic commodity DACs are supposed to only do the digital to analogue conversion and are the cheapest.
Some application dedicated DACs contain a lot more circuitry and save you fpga work e.g. for comms they contain interpolators(3 stages of interpolate by 2 or more), Quadrature modulator, carrier synthesis... in fact it is like a full system rather than just DAC but cost shoots up naturally. Not all aplications need this correction and you can avoid the worst of it by upsampling your signal so that its band is far away from Fs