PCB design / Filter VCCINT, Schedule provided

[Altera_Forum]

Hi there guys, 

 Trying to get some help with the power supply for my PCB for a Cyclone IV-device.  The power-supply design is now finished. I have uploaded the pictures of the schematics. All the “free” capacitors in the upper parts of the pictures will be placed close to the FPGA. My question is now, is it nessesarry to have the filter for VCCINT? How should it be design, what value of the ferrite bead (F1_L1) and capacitor (RC1_C1) should I have?  I now I have specified the Impedance @ Frequency of the bead to 10 ohm @ 100 MHz but that is a guess.  http://imageshack.us/photo/my-images/819/vcca.png http://imageshack.us/photo/my-images/857/vccd.png http://imageshack.us/photo/my-images/163/vccint.png http://imageshack.us/photo/my-images/688/vccio.png  Sorry had problems embedding the pictures!  Kind regards, mr_embedded

[Altera_Forum]

Please don't start new threads with the same questions. 

 http://www.alteraforum.com/forum/showthread.php?t=29904  I sent you links to power supply design documents. You have not provided details showing that you have investigated your design requirements properly.    --- Quote Start ---   My question is now, is it nessesarry to have the filter for VCCINT?   --- Quote End ---  The core supply of the FPGA does not need to be filtered. However, its transient response needs to be within specification.  What is the maximum current on VCCINT this design is expected to operate with? What is the required transient response for a load-step of that load current (the data sheet will have the supply minimum and maximum requirements)? Can your supply meet that requirement?  The load step response for the maximum current draw will be a dip in voltage that is determined by the equivalent series resistance of the capacitors you have selected.  All of this is explained in those documents. You need to answer those same questions for your design.  Cheers, Dave

[Altera_Forum]

First of all, sorry for a re-post here! 

 Your answers have been very comprehensive and advanced. I am probably way too inexperienced to be able to fully use your help. Think I looked for a quick fix, i.e. someone took a look at the attached pictures and said that my design should work just fine, guess it is much more complex than that. I will give it a try, to investigate the requirements.     --- Quote Start ---   What is the maximum current on VCCINT this design is expected to operate with?   --- Quote End ---    From PowerPlay Power Analyzer: Core Dynamic Dissipation: 0.5 mW Core Static Dissipation: 50 mW  That is sort of the only data I've managed to acquire.    --- Quote Start ---   What is the required transient response for a load-step of that load current (the data sheet will have the supply minimum and maximum requirements)?   --- Quote End ---    Looked over the Cyclone IV datasheet without any success here.    --- Quote Start ---   Can your supply meet that requirement?   --- Quote End ---   I've used same LDO Regulator as used on Terasic's dev-kit. The datasheet gives an example where a load change of 1.4 A will give a diff of 2.2 % Voltage, with a 10 uF ceramic cap.    --- Quote Start ---   The load step response for the maximum current draw will be a dip in voltage that is determined by the equivalent series resistance of the capacitors you have selected.   --- Quote End ---   I have 17 ceramic Caps. From Wikipedia ESR per cermaic cap is < 0.015.  17*0.015 = 0.255 Ohm. How can I use this?  Did you see the picture of the power supplies. Do you think it is necessary to have all those caps close to the FPGA?  Regards, mr_embedded

[Altera_Forum]

--- Quote Start ---   Your answers have been very comprehensive and advanced. I am probably way too inexperienced to be able to fully use your help.   --- Quote End ---  The best way to learn, is to ask how others do things. But then you have to try it too; even if you get the wrong answer, at least you are on the path to learning something new.    --- Quote Start ---   Think I looked for a quick fix, i.e. someone took a look at the attached pictures and said that my design should work just fine, guess it is much more complex than that. I will give it a try, to investigate the requirements.    --- Quote End ---  Next time post schematic pages in PDF format. Looking at snapshots of diagrams on a crappy website that has pop-ups is a pain. No-one will help you.    --- Quote Start ---   From PowerPlay Power Analyzer: Core Dynamic Dissipation: 0.5 mW Core Static Dissipation: 50 mW  That is sort of the only data I've managed to acquire.   --- Quote End ---  This analysis is incorrect. You need to implement a 'typical' design, run modelsim to obtain a value-change-dump (.vcd) file (I think thats the right name), and then run that through PowerPlay. Its a pretty memory intensive process when it comes to large devices, so what I've done in the past is to create a design with banks of toggle registers. I implement a design containing a number of these registers controlled by a generic, and then get power estimates for 10%, 20%, 30%, etc, and then extrapolate to 100%. This can then be considered your worst-case design power load.    --- Quote Start ---   Looked over the Cyclone IV datasheet without any success here.   --- Quote End ---  Its design dependent, so you have to analyze it.    --- Quote Start ---   I've used same LDO Regulator as used on Terasic's dev-kit. The datasheet gives an example where a load change of 1.4 A will give a diff of 2.2 % Voltage, with a 10 uF ceramic cap.   --- Quote End ---  An evaluation board is by definition for 'evaluation'. There is no guarantee that that board could supply power to the worst-case design you can come up with.    --- Quote Start ---   I have 17 ceramic Caps. From Wikipedia ESR per cermaic cap is < 0.015.  17*0.015 = 0.255 Ohm. How can I use this?   --- Quote End ---  You need to read the documents and references :)  The ESR of the bulk decoupling is important. The ESRs work in parallel, i.e., if the ESR of a single cap is 15milli-Ohms, and I have 3 of them, then their effective ESR is 5milliOhm. If you have a load step of 1A, then expect to see a supply drop of 5mV. The FPGA core voltage requirements need to consider this load step voltage change, and any voltage ripple from the power supply, eg., a switch-mode supply generally has a rippled voltage.    --- Quote Start ---   Did you see the picture of the power supplies. Do you think it is necessary to have all those caps close to the FPGA?   --- Quote End ---  The high-frequency capacitors should be as close as possible to the power pins on the FPGA. For BGA devices, I use via-in-pad and place the capacitors on the back-side of the board right on the vias that lead to the BGA pins. However, my designs can implement load steps of 15A per FPGA, so are at the extreme end of the scale. You want to get them as close as possible to the power pins (between a power and ground pin if you can, or drop a via to the ground plane as close to the capacitor ground pad as possible).  The 10uF capacitors can be placed as close as is convenient to the FPGA.  Cheers, Dave

[Altera_Forum]

Thanks one again, 

From what I understand, I need to finish the FPGA design in order to make a reliable Power Analyze. I will put the whole PCB on hold for a while and do it all over again later on, and also do it more thoroughly. Hopefully will you see me upload a PDF in a couple of weeks hehe :)  Have a great one and thanks.  Regards, mr_embedded

[Altera_Forum]

--- Quote Start ---   From what I understand, I need to finish the FPGA design in order to make a reliable Power Analyze. I will put the whole PCB on hold for a while and do it all over again later on, and also do it more thoroughly.   --- Quote End ---  Board designs that include FPGAs are iterative in that you first need to have an idea, then implement an initial version to determine what size FPGA you need, the support logic (external memory etc), and I/O. Then you start the board layout, and determine what is feasible in reality. Then go back and adjust your FPGA design as needed.  So don't be too concerned that you have to put the PCB design on hold, its just part of the process. You've now realized that the power supply design depends on what is operating inside the FPGA. You can either design a power-supply for the worst-case design, or design it for the design you expect to use. If you design for the worst-case, then you might get the PCB job done quicker, but the power-supply designs will be higher-current, and more expensive. So its a trade-off, and its a trade-off only you can make.  Cheers, Dave

[Altera_Forum]

Dave, 

Ye you I think that maybe the most important lesson here is what you described. I've changed the strategy slightly. Will still send my present design to PCB manufacturer and test it in action and put the extensive design of the power supply on hold until I've further investigated the design and also how the present design works.  So far, thanks!  Regards, mr_embedded

[Altera_Forum]

--- Quote Start ---   I've changed the strategy slightly. Will still send my present design to PCB manufacturer and test it in action ...   --- Quote End ---  If your design has switch-mode power supplies on it, then make sure there are resistors, or resistor pads, in the feedback path of the power supply. These pads would be used to inject a sinewave into the supply so that you can get a bode plot of the frequency response. You can then use that information to adjust the power supply feedback network to obtain an optimal transient response. The power supply design document, and the board schematic I referenced you to, have examples.  If you're using a power supply module, you might not be able to do this, but if you can it is useful for board bring-up.  Another good reason for using ferrite beads on power supplies is that you can remove them and replace them with a lab power supply. This can help debug problems. The ferrite beads can also be removed when you are tracking down a power supply short, eg. a decoupling capacitor that has rotated and shorted out power-and-ground.  Cheers, Dave

[Altera_Forum]

Dave, 

I did place pads for ferrite bead so I can try a bunch of them. Hopefully will I be able to post the PDF of a working design and description about the process later on, like you did!  Thanks a lot!  Regards, mr_embedded