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PCIe HIP Cyclone 5 i/o timings

APack
Beginner
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Hi I was wondering if someone could tell me the sort of timings they would expect performing basic BAR read/writes using the hard IP? Measuring from the software driver we are getting up to 2us to do reads. If I look internally at the avalon bus signals I have attached to it it looks like the transaction takes may a 100ns or so, obviously I can't signaltap the IP. Does anyone have any idea as to what times we should expect? I will probably have to move BAR space into a DMA if we can't figure out the latency.

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Nathan_R_Intel
Employee
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Currently, there is no measurement to the level of identifying the timing for BAR read/write using the hard IP.

 

 

Regards,

Nathan

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