PCIe Refclk differential pairs pin-connetion problem

[Altera_Forum]

PCIe Refclk differential pairs pin-connetion problem 

  Hello,   Now I have an already-made PCB board with an EP4GX50 device in F484 package and I'm repalnning the pin assigments of the PCIe example design according to my board.   The compilation goes wrong and this is the error message.    Error (176559): Can't place MPLL or GPLL PLL "top_example_chaining_pipen1b:core|top_plus:ep_plus|top:epmap|top_serdes:serdes|top_serdes_alt_c3gxb_lce8:top_serdes_alt_c3gxb_lce8_component|altpll:pll0|altpll_nn81:auto_generated|pll1" in PLL location PLL_5 because I/O cell "refclk" cannot be placed in I/O pin Pin_M7 (port type INCLK of the PLL)    I find this below in the Cyclone IV Device Handbook.   http://www.alteraforum.com/forum/attachment.php?attachmentid=11598&stc=1    According to this, PCIe Refclk differential pairs can only connect to REFCLK2 or REFCLK3 or both? The already-made board has ignored this, connecting them to REFCLK0 In Bank 3B. Is there any solution to pass the compilation and make the board work properly with the PCIe example design, without remake the PCB board?   Best Regards, Cycad Hsu

[Altera_Forum]

Because of the structure of the Cyclone IV, basically, no. There isn't a way of fitting the design unless you can move the clock onto REFCLK2. 

 Sometimes it is possible to use a second PLL. You use one to drive the signal onto the GCLK network, then feed that clock as the reference clock for your PCIe core (which in turn connects to the PLL for the PCIe). However in the Cyclone IV, the datasheet leads me to believe that this would not work. You could try it, but I doubt the design would fit.

[Altera_Forum]

I think you're right cause I find a note that "Clock output from PLLs in the FPGA core cannot feed into PLLs used by the transceiver as input reference clock." So I'm gonna redraw the PCB board. 

 Thanks

[Altera_Forum]

I suppose the take away from the experience is (a lesson I learnt the hard way too), always test compile the design with your pin assignments before sending the board off to manufacture.