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I need to know which Intel FPGAs/SoCs supports more than one VC?
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Thanks Nathan!
What I don't get is, why then, in all the documentations for the Avalon Interface the 7 VCs are mentioned?
They always describe the "Address Map of Hard IP Configuration Space Registers", where VC0-VC7 is mentioned. Is there any way to access to this configuration space registers?
E.g. for the V-Series:
https://www.intel.com/content/www/us/en/programmable/documentation/nik1410905927419.html
Another question: Which Intel FPGAs/SoCs supports more than one TC (Traffic Class)?
Thanks in advance!
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Thanks again Nathan!
Answer:
For now Arria V, Arria 10, Cyclone V, Cyclone 10, Stratix V and Stratix 10 devices support more than one TC.
=> Sorry but I forgot to ask before: Are these multiple TCs available for the outgoing traffic or only for the ingoing traffic or both?
Thanks in advance!
Julian
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The multiple TCs are for both.
Regards,
Nathan
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