we are using stx10 1SM21BHU2F53E2VG and 1SG10MHN3F74C2LG at both there is PCIe IP
we encounter an error while programing the fpga , if the 100Mhz reference clock is not supplied from the HOST at the programing stage .
is there any way to program the FPGA without the ref clock , and supply it only after programing ?
in details: the new computers does not supply the reference clock if they does not detect pcie device , therefore the programing of the FPGA fails , on the other hand , we can not program the FPGA since it seems that it does not receive the ref clock - any idea how to solve this deadlock ?
Do you mean to connect the refclk pin to internal FPGA generated clock? The input reference clock, refclk, must be stable and free-running at device powerup for a successful device configuration.
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
I'm trying to collect more data and snapshoot to in order to provide more details about the issue .
the issue is complex to explain -
in general , the once the REF clock of the PCIe is not working , the programing/burning the fpga and the of the PCIe Serdes (the Phy) is not done .
if it is better to close this issue , and later on I will open new one , or this one , it is ok from my side.
Thanks for your permission to close this case.
Hence, This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you
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please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.