PCML and LVDS clocks, and fitter placement error

[Altera_Forum]

I inherited code for high-speed serial data transfer on the Terasic Cyclone V GX dev board. The 1 Gbps link is done with a GXB_RX block (Cyclone V Transceiver Native PHY IP), and the rx_cdr_refclk port of that block is driven by a 125MHz 1.5-V PCML clock (called REFCLK_P0) that's generated on the dev board. 

 I'm porting that code to the Altera Cyclone V GT dev board. The GT dev board does not have an on-board 125MHz PCML clock. Instead, it has a 125MHz LVDS clock (called clk_125m_p and tied to pin U31 on the C5GT fpga). When I try to use this LVDS clock in the GXB_RX block (for rx_cdr_refclk), the fitter fails (error message below).  Can you suggest any ways to use the LVDS clock to drive the GXB_RX block?  -- many thanks for your help     --- Quote Start ---  Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s))  Error (175020): Illegal constraint of pin to the region (121, 60) to (121, 95): no valid locations in region  Info (14596): Information about the failing component(s):  Info (175028): The pin name(s): clk_125m_p  Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:  Error (175005): Could not find a location with: HSSI (1 location affected)  Info (175029): pin containing PIN_U31  Info (175015): The I/O pad clk_125m_p is constrained to the location PIN_U31 due to: User Location Constraints (PIN_U31)  Info (14709): The constrained I/O pad is contained within this pin Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter. Error (11802): Can't fit design in device  --- Quote End ---  

[Altera_Forum]

For Stratix V's (not sure about Cyclone V's), the only way to use an LVDS clock to drive the transceivers is for it to be one of the dedicated clock inputs that can drive the Fractional PLL Strip on the in the same corner that the transceiver is in. 

 The other option is you drive the clock into one of the GX Transceivers and configure the design to use that as the dedicated clock, but to do that you need to drive the clock into either RX1 or RX4 in a transceiver bank (again based on knowledge of Stratix V, not Cyclone V).

[Altera_Forum]

Which HSMC bank are you using? As far as I can tell (guessing which dev kit you have), if you are using HSMC Bank A, then there is a dedicated Reference clock pin (REFCLK_QL2_P/N) which is connected to Oscillator X3. This is a programmable oscillator which is by default 148.5MHz, but can be reconfigured to anywhere between 10MHz and 810MHz, so it may be worth looking in to whether it can be made to do 125MHz. Alternatively, if you are using HSMC Bank B, you have a 100MHz clock available (REFCLK_QL3_P/N) - could you alter your design to use 100MHz reference instead of 125MHz? 

  Dev Kit Reference Manual: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf

[Altera_Forum]

I'll be using xcvrs on both HSMC ports (A and B ). Indeed, I am using the Dev kit linked to in the post above (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cvgt_fpga_dev_board.pdf) 

 As TCWORLD pointed out, the relevant clocks are REFCLK_QL2_P/N and REFCLK_QL3_P/N (from on-board oscillators X3 and X4).  Using the ClockControl.exe program that came with the Cyclone V GT example software (examples/board_test_system), I was able to set the clock frequency for both oscillators (X3 and X4) to 125MHz. And my code now compiles successfully.  The clock programming via ClockControl.exe is volatile. I'll eventually need to figure out how to make this change stick (if I can't figure out a solution, I'll be back to the forum), but for now I have a way to proceed with the SERDES work.  Many thanks for the replies -- it's invaluable to have this online support.

[Altera_Forum]

If you are using xcvrs across both, it is possible to use just on of the reference clocks (probably X3 as the other one may be useful later on in the project) and then distribute that across both of the transceiver banks using the transceiver internal clock network which should be inferred automatically by clocking a transceiver on one bank with the reference clock of another. Otherwise you will end up with two not necessarily synchronous clocks (e.g. X3 might be 125.00001MHz and X4 could be 124.999999MHz) which could lead to issues.

[Altera_Forum]

Thanks for the good suggestion. I was worried about using two different clocks, but I didn't know about the xcvr internal clock network. I've verified that the code compiles when I use X3 on either HSMC port A or B.