I am currently designing a board with an Arria 10 and I used the relevant PDB tool v19.0.
I am wondering what the clock core frequency refers to. Is it the frequency of the design or the frequency for the core in case of a SOC ? And in this case, what should be the value if there is no SOC in the FPGA ?
This parameter seems to have a huge impact on the count of decoupling capacitor so it's important it should be set properly.
Until now, I have set to Medium.
I've read the Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide. It does explain what this frequency is used for but not what it is and where this information can be found.