PLL CLK OUTPUT I/Os

[Altera_Forum]

I'm using one PLL on my Cyclone III device to generate two CLKs with a 50MHz oscillator as input. From the literature it seems that CLK output c0 can be fed directly to one of the PLL CLKOUT pins. My other clock output is internal but I also wish to make the same clock available externally. Currently I have it assigned to the CLKOUT pin of another PLL on the other side of the device. I'm not sure if this is OK or if there is a better way to generate two external CLK outputs from a single PLL. 

 A related question pertains to board design (termination) for CLK and DATA outputs from the FPGA. Do I need to add external series termination resistors?

[Altera_Forum]

With Cyclone III, you have the option to clock the second PLL from the same input (or to chain PLLs). This option involves additional clock uncertainty and jitter, as when using a non-dedicated clock output. But both variants are probably sufficient for many applications. 

 For maximum clock performance, both PLLs should be clocked directly from an external distribution buffer, preferably with a differential I/O standard.