I have a design which has a 4 IO pin which are all bidirectional. Each IO pin is connected to a IO_MUX. The IOMUX can connect either the output from a register or the output from same PLL clock output c0. In the chip planner, the clock output comes out to a single combinatorial gate then fans out to 4 muxes ( another combinatial ) before heading to the io pin. The issue I have is that becuase all PLL output comes out from a single comb node, the skew between the IO pins is not right. I can move the comb node which has the clock output. Is it possible clock output to appear from multiple combinatorial nodes instead of all the IO_MUXes sharing? Kind of like the max fan attribute but for a PLL output.
