Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18951 Discussions

PLL Output Phase Alignement

SK_VA
Beginner
415 Views

Hi ,

I am using PLL in normal mode in Cyclone iv device.I could see a phase difference between the pll input clock and pll output clock of 3ns. How to minimize the skew such that pll input and output clocks are exactly phase aligned.

0 Kudos
1 Reply
JonWay_C_Intel
Employee
80 Views

Hi @SK VA​ 

 

It depends where your pll output clock is targeted to. You might want to choose a different mode.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51005.pd... (Page 23).

Reply