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Difficulty setting pin Impedance


I'm trying to learn how to implement a 3V LVTTL interface using a Cyclone IV E (EP4CE10) FPGA. However, I would like to ensure that the input/output impedances of the IO is at 50R. I see that it is possible to achieve this In the IO Features guide here on page 7, providing I use column/row IO 4, 8, 12 and 16. However, I am confused as to what the actually means.


Presumably there are only certain IO that can use this feature, but I cannot seem to find which specific pins this applies to.


Reading the Cyclone IV handbook here on page 122 onwards, it talks about banks which I think I understand - but it doesn't tell me which specific pins this applies to - nor do I see anything about 'rows' or 'columns'. Furthermore I can't see how to actually ensure that the input/output Z can be set to 50R.


In short, how can find out which pins I can use and how do I set the impedance on the device?


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From the above I can assume that the impedance that is been briefed is about the OCT . The Table 6-2 give you the setting for the OCT ( page no: 7)

Kindly follow the table .