PLL-Phase relationship

[Altera_Forum]

Hi, 

 does anybody know how to keep the phase relationship with respect to the input clock? The input clock for the PLL2 is the output clock from PLL1. Following the PLL2 settings: Input clock: 48MHz C0: 24MHz, clock phase shift = 5ns, duty cycle = 76%  Every time I power-up the phase relationship between input clock and output clock C0 is different. Does anybody know how to keep always the same phase between input and output clock?  I found out that for some phase shift values the output clock keeps always the same phase shift relationship with respect to the input clock.   I' am using Cyclone II.  Thanks!

[Altera_Forum]

If the input clock is present before FPGA power up, the PLL output should have a defined phase with PLL standard settings, to my opinion. If the PLL looses lock afterwards, respectively the input clock isn't present in time, the phase is undefined and a PLL reset necessary to reset it to defined conditions.

[Altera_Forum]

The input clock for PLL2 isn't ready before FPGA power-up. Only the input clock for PLL1, which output generates the PLL2 input clock, is ready before FPGA power-up. 

I tried to reset (areset) the PLL2 after the PLL1 is locked but I still have different phases between input and output clock.

[Altera_Forum]

--- Quote Start ---  I tried to reset (areset) the PLL2 after the PLL1 is locked but I still have different phases between input and output clock.  --- Quote End ---    If by "input" you mean the clock at the device input pin feeding PLL1 and not at the PLL2 input, then maybe the phase problem is in PLL1. The Cyclone II device handbook says, "The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL input and output clocks." Are you doing this for PLL1, using separate reset signals for PLL1 and PLL2? Even if you think the PLL1 input is running in time for you not to need to reset PLL1, you should check the PLL1 lock status to make sure the problem isn't in that PLL.  Are you using the gated lock so that you know for sure PLL1 is locked before you deassert the reset for PLL2? The ungated lock can be asserted before the PLL is fully locked (device handbook Chapter 7, page 7-19).  Are you cascading the PLLs internal to the FPGA, or are you taking the PLL1 output to a device pin and externally connecting it to an input device pin driving PLL2? The Cyclone III device handbook discusses cascading PLLs, but I didn't find that in the Cyclone II device handbook. When I tried it in Quartus, I got messages about not being able to merge the PLLs. If cascading PLLs internal to the FPGA is not supported, then the PLLs might not behave properly if cascaded through an external connection.