PLL Relock problem

[Altera_Forum]

Hi, 

 i used a pll in EP3C40F484, the pll had two clock input pins and a switch input pin. in my logic, i used switch input to select the input clock (inclk0 or inclk1), however, when i changed switch signal, for example, from 0 to 1, and then gave pll a reset, the pll could not lock again, i saw that the locked output was always 0 in signalTap. did i miss something?   thanks for any answer.   regards, ingdxdy

[Altera_Forum]

Do You use PLL core clock switch option or You just have a mux, which select a clock before PLL input?

[Altera_Forum]

Hi, Socrates, 

i used PLL core clock switch to select the pll clock input, when i dynamically switch the PLL input, it just could not relock again.   regards, ingdxdy     --- Quote Start ---  Do You use PLL core clock switch option or You just have a mux, which select a clock before PLL input?  --- Quote End ---  

[Altera_Forum]

Then read the documentation carefully. Afaik it doesn't switch on switch state change - You need to do a pulse for switching. 0->1 and 1->0.

[Altera_Forum]

Hi, Socrates, 

Sorry for my carelessness and thanks much for your help.:)   regards, ingdxdy     --- Quote Start ---  Then read the documentation carefully. Afaik it doesn't switch on switch state change - You need to do a pulse for switching. 0->1 and 1->0.  --- Quote End ---