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Altera_Forum
Honored Contributor I
1,473 Views

PLL clock switchover with automatic derivation of PLL clocks is not working

Hi all, 

 

I'm using a Cyclone V and need to switch between two input clocks. The clocks have the same parameters. I adhered to the timequest cookbook which says the following: 

 

#create a 10ns clock for clock port clk0 create_clock -period 10.000 -name clk0 # create a 20ns clock for clock port clk1 create_clock -period 20.000 -name clk1 # automatically create clocks for the PLL output clocks# derive_pll_clocks automatically makes the proper# clock assignments for clock-switchover derive_pll_clocks set_clock_groups -exclusive -group {clk0} -group {clk1} 

 

But now Quartus tells me it can not derive the master clock for the PLL and therefor it can not derive any of the PLL output clocks. 

 

Warning (332087): The master clock for this clock assignment could not be derived. Clock: |altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph was not created. Warning (332036): Clock: clk0 found as a potential master clock candidate Warning (332036): Clock: clk1 found as a potential master clock candidate 

 

By constraining PLL input and output clocks manually I can make it work. Quartus/Timequest then recognizes alle the clocks correctly. But this is way to much work to repeat it for every new project... 

 

Has anyone experience with this kind of issue? 

 

Thanks in advance, 

 

Sören
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7 Replies
Altera_Forum
Honored Contributor I
112 Views

How are you selecting the input clock to the PLL? That logic may be why derive_pll_clocks isn't working. Can you post the HDL code? Normally, clock inputs make direct connections to PLLs.

Altera_Forum
Honored Contributor I
112 Views

Thanks for your reply! 

 

Both clocks are connected directly to the PLL. From dedicated clock input pins of the FPGA to "refclk" and "refclk1" inputs of the PLL. To switch from one clock to the other I'm using the clock switchover feature of the PLL. So my logic isn't really involved in that whole clock thing. Its job is just to set the "extswitch" input of the PLL to logic '1' for a certain time whenever I want to switch the clocks. Until that the PLL defaults to "refclk".
Altera_Forum
Honored Contributor I
112 Views

No ideas? Do you need more information to give an qualified answer? Then please tell me what you need.

Altera_Forum
Honored Contributor I
112 Views

Hmm. Have you created your base clock constraints correctly? What happens if you comment out your base clocks and use the -create_base_clocks option with derive_pll_clocks?

Altera_Forum
Honored Contributor I
112 Views

Sorry for the late answer. I've been at home with the flu since last week... 

 

I'm quite sure my base clock constraints are correct. Here they are: 

 

create_clock -name {clk0} -period 100.000 -waveform { 0.000 50.000 } create_clock -name {clk1} -period 100.000 -waveform { 0.000 50.000 }  

 

Nevertheless I tried what happens without them but with the -create_base_clocks option. The result is still the same. But now, according to the "clock summary" report, Timequest does not even know my base clocks. 

 

After this I disabled the clock switchover option of the PLL and adapted its instantiation in my HDL accordingly. No other changes. Synthesized. Works. Base clock is known and PLL clocks also. 

 

So what I know so far is: 

  • It works for a single clock and for two clock sources if I write all constraints by hand. Base clocks, PLL input and output clocks and clock groups. 

  • It works for a single clock if I use the derive_pll_clocks command intead of constraining it by hand. Using -create_base_clocks option has no influence. 

  • It does not work for two clock sources if I use the derive_pll_clocks command intead of constraining it by hand. Using -create_base_clocks option has no influence. 

 

 

So far, so bad...
Altera_Forum
Honored Contributor I
112 Views

get_ports arguments should be the name of your clock ports from the timing netlist (i.e. your design), not the names of the pins themselves. You had it correct in your original post above. 

 

And what are your PLL parameter settings?
Altera_Forum
Honored Contributor I
112 Views

These are the names I used in my design. I named them after the actual pin names of the FPGA. Is it possible that Quartus is confused therefore? 

 

I'm not sure which PLL parameters you mean. I attached a file with the counter settings and some other parameters. (https://www.alteraforum.com/forum/attachment.php?attachmentid=13357 ) If you need to know other parameter settings just let me know.
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