PLL dedicated external clock output pins in cyclone II EP2C20F484c7 FPGA

[Altera_Forum]

hi all, 

  I am using Cyclone II FPGA Starter Development Board which contains cyclone ii ep2c20f484c7 FPGA to drive 800*480 color LCD. For external interface with LCD, i am using the two 40 pin expansion headers. I am not using the on board VGA video port.   LCD requires a clock input of 33 MHz from FPGA. So, i require an external clock output from FPGA. I am using ALTPLL megafunction to generate this. However, while compilation, it shows a warning that use pll dedicated external clock output pins, otherwise skew performance is not guaranteed. How can i select this option in ALTPLL megafunction which has three clocks c0,c1,c2. In schematics of board, it shows that PLL dedicated external clock pins are differential and i need a single ended 3.3V LVTTL compatible clock. How can i do this?    thanks in advance,  praveen

[Altera_Forum]

You should use the pin that is connected to LCD clock input, if it's dedicated clock output or not. If it's a dedicated clock output, it can be used also with single ended IO standard.

[Altera_Forum]

Actually, ALTPLL megafunction is having c0,c1,c2 as PLL clock outputs for cyclone II EP2c20F484c7. The dedicated PLL clock output pins are (PLL1_OUTp, PLL1_OUTn), (PLL2_OUTp, PLL2_OUTn), (PLL3_OUTp, PLL3_OUTn), (PLL4_OUTp, PLL4_OUTn) (differential output). 

  I have access only to the two 40 pin expansion headers(which connects 72 FPGA pins) since it is a starter board. (PLL2_OUTp, PLL2_OUTn) pins are connected to one of the expansion headers. So, i tried to assign PLL2_OUTp pin to PLL clock output c2 since i need only single ended o/p & c2 is the clock output which drives the external clock o/p. Still, the same warning comes while compilation   warning: pll "pll:u3|altpll:altpll_component|pll" output port clk[0] feeds output pin "c2" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use pll dedicated clock outputs to ensure jitter performance   Please give your suggestions on this.

[Altera_Forum]

With Cyclone II, PLL2 could be only used when clocked by a connected dedicated clock. I think, no clock is connected to PLL2 dedicated inputs with the starter board. If I'm right, PLL2 clock output couldn't be used. But I wouldn't overrate the said warning. The clock is usable with defined timing anyway.