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Altera_Forum
Honored Contributor I
1,019 Views

PLL error in BeMicro Max10 FPGA Evaluation Board

Hi All, 

 

I use BeMicro Max10 FPGA Evaluation Board. I need to verify the inbuilt ADC inside Max10. But I got following warning and error regarding the Avalon ALTPLL  

connected to the ADC. 

 

Warning (15058): PLL "max_adc:max_adc_inst|max_adc_adc_pll:adc_pll|max_adc_adc_pll_altpll_5q22:sd1|pll7" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins 

 

Error (170084): Can't route signal "max_adc:max_adc_inst|max_adc_adc_pll:adc_pll|max_adc_adc_pll_altpll_5q22:sd1|wire_pll7_clk[0]" to atom "max_adc:max_adc_inst|max_adc_modular_adc_0:modular_adc_0|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|primitive_instance" 

 

Thanks, 

Musthafa
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3 Replies
Altera_Forum
Honored Contributor I
54 Views

Hi, 

i'm chiming in here with the same issue. Please let me know if you solved it! 

Best, 

K
Altera_Forum
Honored Contributor I
54 Views

SNigg1
Beginner
54 Views

Not helpfull since link is not working anymore

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