PLL for clock scaling.

[Altera_Forum]

Hello, 

 as a newbie I'd like to ask you for some understanding and patience. Was not sure where this question should be posted, so please move it/tell me to move it if you find appropriate.  I want to build a simple UART on my FPGA. I've been told to try to use a PLL for prescaled clock for my design. However, I am not sure how do I make it work.  I have generated a PLL with desired frequency output clock, but now I am not sure where should I put it in my design. Should I enclose it together with my uart to make a top-level entity? Or should I assign it somewhere/use it's output in some assignment to connect it to my uart-entity's clock?  I use Quartus II Web Edition trying to synthesise design for Cyclone V.  Thank you for any tips. Kuba

[Altera_Forum]

You can directly connect the PLL output clock to your module at top level RTL.

[Altera_Forum]

Alright, I created another top-level entity enclosing the generated PLL entity and my own receiver. It appears to make sense now (please tell me if this is incorrect.) 

 Thanks!