PLL lock problem

[Altera_Forum]

Hi all, 

 I have problems with the PLLs in a 5CGXFC7D6F31C6N. They don't lock. I can reduce my design to 4 PLLs as shown here:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8150   The first PLL locks alwys and the other ones never. Is the connection like this ok? What parameters should I use for the different PLLs? Altera recommends low badnwidth for the first and high bandwidth for the cascading PLLs, but that doesnt' help. Does anyone else experience problems with the Cyclone 5 PLLs?  I tried almost every combination and location assingment but never every PLL worked.  Any idea why this doesn't work?  The only not so good thing is that we share one 2.5V power plane for everything which means VCC_AUX, VCCPDx, VCCH_GXBL and VCCA_FPLL. But as there are no other outputs and nothing else in the design it shouldn't be such a problem.  And they NEVER lock. Not even for a short moment or so.  Thanks!

[Altera_Forum]

Hi, 

One ALTPLL has about 5 outputs, since you are using the same reference frequency to generate the out freq., why don't use a single ALTPLL? instead of 4 PLLs.  Regards, Uday

[Altera_Forum]

--- Quote Start ---  Hi, One ALTPLL has about 5 outputs, since you are using the same reference frequency to generate the out freq., why don't use a single ALTPLL? instead of 4 PLLs.  Regards, Uday  --- Quote End ---    Actually, one of the Cyclone 5 PLLs has up to 9 outputs. But the generated frequencies are restricted to a common divider. If you need frequencies which don't match this criteria you need different PLLs.  However, I solved my problem above, I forgott to connect a resistor to the RREF pin which then led to this very strange behaviour.  Oliver