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PLL not fully compensated because it is fed by a non-dedicated input


Hello everybody,


I am having problem with error messages about the PLL:

Warning (15062): PLL in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register

Warning (15055): PLL input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input


This is a Max10 10M02SCU169 device with LVDS clock connected to E13/F13 pins (this are the clk3p/clk3n pins which are GCLK capable). I am not sure why am i getting this error. I checked the Technology Map View of my design (see image attached) and i notice Quartus inserted a CLKCTRL block in the clock line. I assume this is the problem for the warnings, but i am not sure why is this block there. In my code, the PLL is fed directly from LVDS input.


I notice there was a similar thread about this ( ), but i was not able to find the cause of the problem.

Does anybody have an idea what is the problem.




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Let me answer to myself. The problem is that the this device has only one PLL, not two as i assumed from the M10 Overview - Table4. The PLL1 has to be connected to ckj0/clk1 input to be fully compensated, but in my case it is connected to clk3.