PWM outputs spike on startup of MAX10

[Devin2]

I am using the PWM outputs on a MAX10 FPGA (the 10M50SAE144C8G) as triggers for the gate drivers in my H bridge circuit. I'm finding that on initial powerup of the circuit before my software starts running, the FPGA is producing voltage spikes with seemingly random timing. This could cause current shoot through on my H bridge if the wrong ones turn on at the same time. Are there any configuration settings in Quartus or a software approach that would keep the PWMs low during startup?

[FvM]

Hi,
FPGA pins are connected to weak pull-up resistors during power-on reset until the user mode configuration is active. The only way to avoid unwanted high level is to connect pull-down resistors. Minimal pull-up value for 3.3V VCCIO is 7k according to datasheet, you can calculate appropriate pull-down resistor value according to maximal logic low level of connected device.

1 - 2.2k should work in most cases.

[AqidAyman_Intel]

Hello,

For more information on the Power-On Reset circuitry in Max 10, please refer to the link below:

https://www.intel.com/content/www/us/en/docs/programmable/683400/18-0/power-on-reset-circuitry.html

Regards,

Aqid

[AqidAyman_Intel]

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[NameGad]

I was lucky enough to find this place. The same problem also occurred in my MAX10 FPGA (10M50SAE144C8G) project today. I successfully solved the problem by combining the following two documents.

https://www.intel.com/content/www/us/en/docs/programmable/683400/18-0/power-on-reset- Circuitry.html  and

https://www.ntchip.com/Datasheets.aspx?PDFfile=/Datasheets/IntegratedCircuits/m10_datasheet.pdf&brandpartno=Altera/10M50SAE144C8G