Partial reconfiguration CRC error

[Altera_Forum]

I am using Stratix V FPGA, and using the partial reconfiguration feature while I got the CRC error when I do the partial reconfiguration. 

 FPGA is connected with CPU through PCIe interface. My software read the rbf file and write the data to a customized MMIO register in FPGA. The verilog code behind the register will transfer the data to the partial configuration control block to do the reconfiguration.  When the partial reconfigured logic is simple, like just doing (data_out <= data_in + 1) things, every things are ok. I really see the functions changed in the reconfigured logic. So it means my way to use the partial configuration control block is correct. When the partial reconfigured logic is much more complex, the CRC error is reported when being reconfigured.  I will tell you what have I tried: 1. Using the Partial Reconfiguration IP core from IP Catalog.  a ) I try 32 bit data, 16 bit data, 8 bit data. The result is the same.  2. Using the stratixv_prblock and stratixv_crcblock primitives in my verilog code instead of using the IP core.  3. Using the JTAG programmer to do the partial reconfiguration instead of using PCIe to transfer the rbf file.  All of above solutions have the same result. When the logic is simple, every things are ok. When the logic is complex, CRC error happens.

[Altera_Forum]

good morning Alare, 

Just wanted to get more information about your problem. Im familiar with partial reconfig but it seems it sound a little different from how you are using it. The way i use partial reconfig is by using the CVP method on the PCIe ip core. This allows for reconfiguration of the FPGA through two methods, Initialization mode and update mode. This will require for you to create a persona for the jic and rbf file. you then tell the driver on the PC to load the rbf file. IF you could post more info on how your planning to use it we can try to figure out. Thanks!  -Trukng

[Altera_Forum]

Thanks for your help. I heard about CVP but not use it before. Beside the PCIe IP core, there are static logic inside the FPGA, and two reconfigurable regions ( or you call them partitions). Each such region has multiple personas and I want them to be configured at the run-time. When one region is being reconfigured, the other region can be still running normally.

[Altera_Forum]

I've been wanting to try what you said but haven't been able to. It seems like a useful feature to have. I've spoken to altera regarding partial reconfigure and they have problems themselves when using it. I believe there is something wrong on the dye thats causing the issue u mentioned. The latest sv boards have the fix for it. Sorry I couldn't help with your problem. :(

[Altera_Forum]

--- Quote Start ---  I've been wanting to try what you said but haven't been able to. It seems like a useful feature to have. I've spoken to altera regarding partial reconfigure and they have problems themselves when using it. I believe there is something wrong on the dye thats causing the issue u mentioned. The latest sv boards have the fix for it. Sorry I couldn't help with your problem. :(  --- Quote End ---    The partial reconfiguration require a license that you must pay extra money for. I can't believe that Altera announce its partial reconfiguration support when there is a such obvious bug, although not many people use it in product environment.   Actually, the problem is really easy to replay. I now confirm that the problem has some relationship with the block RAM usage. When you use a FIFO, and/or a shift-RAM in the reconfigured region, you have 99% probability to get that problem. If you don't use any RAM in the reconfigured region, no matter how many percentage resource you are using, there is no CRC error reported.  Dose the "The latest sv boards" you mentioned mean the latest batch of SV chips? So if I buy a new FPGA card with the latest chip, it will solve my problem, right?

[Altera_Forum]

I was able to request a beta version of the partial reconfiguration license and was able to test the feature. I ran into a problem which I had altera try to troubleshoot and the guy helping me said that their latest builds have resolved many of these crc issues. I was trying to perform cvp but kept failing because of this error. I had to run it a few times before it actually worked. I yet to try it on a current sv chip but I'm sure altera will say they have fixed it :) sorry my post didnt help resolve your problem.

[Altera_Forum]

--- Quote Start ---  I was able to request a beta version of the partial reconfiguration license and was able to test the feature. I ran into a problem which I had altera try to troubleshoot and the guy helping me said that their latest builds have resolved many of these crc issues. I was trying to perform cvp but kept failing because of this error. I had to run it a few times before it actually worked. I yet to try it on a current sv chip but I'm sure altera will say they have fixed it :) sorry my post didnt help resolve your problem.  --- Quote End ---    Thanks, you dose help me, or else I will spend another 15 days to seek for an answer that will never come out :-)  Now, I am just hoping that when the crc error happen, there is a way to recover the chip online. Currently, when the CRC error happen, you can not partial reconfigure FPGA anymore. Sometimes even using JTAG to refresh the whole FPGA dose not work. The only way you can do is power-off your machine, and boot the machine again so that the FPGA is configured from the external flash storage. You know it is really bad for me because the machine is shared by a lot of people (that's why I want partial reconfiguration online), I have to email to every body to ask them to save their work before I power off the machine.