Passive Serial & Fast Passive Parallel Configuration for Cyclone IV

[Altera_Forum]

Hi, 

 Can any one guide me to get the 'C' Source code to perform a PS and FPP configuration for my Cyclone 4 device. I am using a freescale processor & an external flash memory.    Basically I am looking for source code that the microprocessor can execute to configure the FPGA device via PS ot FPP configuration. Also I would need the configuration source code to configure via JTAG interface.   Thanks a lot in advance !!!   Thanks, Sunil.

[Altera_Forum]

Hi, 

 Some info for you if you want to configure via JTAG interface https://www.altera.com/download/legacy/jam/dnl-8051_player.jsp

[Altera_Forum]

Hi, 

 Thanks for your reponse. But, I am looking for the C Source code which does the FPGA configuration using the host proecessor !   Thanks, Sunil

[Altera_Forum]

I did this recently for cyclone iii so I will outline the steps. This is for parallel loading scheme.  

 - Convert SOF into a TTF and RBF and select the programming mode. TTF is a comma separated value text file. RBF is a raw binary file. I used rbf becuase it smaller file size and easier to work with in C/C++. - DRIVE DCLK LOW - DRIVE NCONFIG HIGH  - DRIVE NCONFIG LOW  - DRIVE NCONFIG HIGH  - Sleep 1 ms (Delay to allow NSTATUS to pull high) - CONF_DONE should be LOW and NSTATUS shoud be high - For each byte in the rbf file, drive data to fpga data config inputs and pulse DCLK hi - While loading CONF_DONE should remain low / NSTATUS should remain high - After all bytes are loaded pulse DCLK a few extra times (read data book on device for specific extra clocking requirements ). - To verify config if complete/success verify CONF_DONE is high and NSTATUS is high. - Optionally cpu can monitor the NSTATUS pin for errors (Goes LOW), however it can be ignored util the end of loading the entire file to the part.

[Altera_Forum]

Hi kito, 

 Thanks for your response. I will try it out.  Thanks, Sunil

[Altera_Forum]

Hi Kito, 

 Have you ever done this with an SOF and an ELF?