Pin assignment help needed

[Altera_Forum]

Hello, 

I am new to quartus and would require help with the pin assignment feature(using pin planner). I have created a certain design. In the design it is required that certain inputs are always high and certain are always low. I thought of connecting the high inputs to VCC and low to ground. But when I wanted to make that assignment I find that the pins which are shown by in the pin planner layout as vcc or ground cannot be accessed in the location column(The place where the pin number is written). Is there any other way I can assign a permanent high or permanent low to the inputs. I am using the Altera Cyclone 3 FPGA starter kit. I would highly appreciate some inputs.  Thanks and Regards Ranjan Banerjee

[Altera_Forum]

If you have need for signals to be constant "1" or "0", then those don't belong to your design top level input list; they should be constants within your design.

[Altera_Forum]

Here's my 'basic' top-level design for the Cyclone IV GX Transceiver Starter Kit (C4GXSK). I assume that is the kit you are using. 

 EDIT: oops, i re-read your post and you say cyclone 3 in it, sorry. anyway, this type of 'basic' template is what i create for every fpga board design.  Note the warnings regarding the shared address/data bus. The LCD voltages can damage the FPGA if you do not drive the signals.  Cheers, Dave    -- ---------------------------------------------------------------- -- c4gxsk/cyclone4/basic/src/c4gxsk.vhd -- -- 3/6/2012 D. W. Hawkins (dwh@ovro.caltech.edu) -- -- Altera Cyclone IV GX Transceiver Starter Kit basic design. -- -- This basic design implements the following; -- -- * LED connected to PB -- * LED blinked by a counter clocked by the 50MHz osc -- * LED blinked by a counter clocked by the 125MHz osc -- -- This top-level design file can be used as the template for all -- C4GXSK designs. This design file defines the pin directions -- for all devices on the board (including the unused devices). -- -- ---------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; -- ---------------------------------------------------------------- entity c4gxsk is port ( -- -------------------------------------------------------- -- CPU reset (push button) -- -------------------------------------------------------- -- cpu_rstN : in std_logic; -- -------------------------------------------------------- -- Clocks -- -------------------------------------------------------- -- -- 50MHz oscillator clkin_50MHz : in std_logic; -- 125MHz oscillator clkin_125MHz : in std_logic; -- -------------------------------------------------------- -- User I/O -- -------------------------------------------------------- -- -- Push buttons pb : in std_logic_vector(1 downto 0); -- LEDs led : out std_logic_vector(3 downto 0); -- -------------------------------------------------------- -- Flash/SRAM/MAX II/LCD (FSML) -- -------------------------------------------------------- -- -- Flash select flash_ceN : out std_logic; -- SSRAM controls ssram_clk : out std_logic; ssram_ceN : out std_logic; ssram_beN : out std_logic_vector(1 downto 0); -- MAX II select max2_csN : out std_logic; -- LCD select lcd_csN : out std_logic; -- Common controls fsml_oeN : out std_logic; fsml_weN : out std_logic; -- Address/data buses fsml_addr : out std_logic_vector(23 downto 0); fsml_dq : inout std_logic_vector(15 downto 0); -- -------------------------------------------------------- -- Ethernet PHY -- -------------------------------------------------------- -- -- Reference clock refclk_enet : in std_logic; -- Reset enet_rstN : out std_logic; -- Interrupt enet_intN : in std_logic; -- Management I2C interface enet_mdc : out std_logic; enet_mdio : inout std_logic; -- PHY interface -- enet_tx : out std_logic; -- enet_rx : in std_logic; -- -------------------------------------------------------- -- PCIe -- -------------------------------------------------------- -- -- Reference clock refclk_pcie : in std_logic; -- Reset pcie_perstN : in std_logic; -- Transceivers -- pcie_tx : out std_logic; -- pcie_rx : in std_logic; -- -------------------------------------------------------- -- EPCS (serial EEPROM) interface -- -------------------------------------------------------- -- epcs_clk : out std_logic; epcs_csN : out std_logic; epcs_mosi : out std_logic; epcs_miso : in std_logic ); end entity; -- ---------------------------------------------------------------- architecture basic of c4gxsk is -- ------------------------------------------------------------ -- Parameters -- ------------------------------------------------------------ -- -- Clocks constant CLK_FREQUENCY_A : real := 50.0e6; constant CLK_FREQUENCY_B : real := 125.0e6; -- Counter count required for ~0.5s pulse time on first LED constant CVALUE_A : real := 0.5*CLK_FREQUENCY_A; constant CVALUE_B : real := 0.5*CLK_FREQUENCY_B; -- Counter width required constant CWIDTH_A : integer := integer(ceil(log2(CVALUE_A-1.0))); constant CWIDTH_B : integer := integer(ceil(log2(CVALUE_B-1.0))); -- Note: -- The counter count widths are the number of bits required -- to count for about half a second. This essentially rounds -- the count up to the nearest power-of-2, so the two LED -- blink periods will not be the same. -- -- When viewing the hardware, you can see the effect of this -- rounding as the slight difference the relative timing of -- the two LEDs. -- ------------------------------------------------------------ -- Signals -- ------------------------------------------------------------ -- -- Reset (rename the external signal) alias rstN is cpu_rstN; -- Counter signal count_a : unsigned(CWIDTH_A-1 downto 0); signal count_b : unsigned(CWIDTH_B-1 downto 0); begin -- ------------------------------------------------------------ -- Push-buttons to LEDs -- ------------------------------------------------------------ -- led(1 downto 0) <= pb; -- ------------------------------------------------------------ -- LED counters -- ------------------------------------------------------------ -- -- 50MHz clock process(clkin_50MHz, rstN) begin if (rstN = '0') then count_a <= (others => '0'); elsif rising_edge(clkin_50MHz) then count_a <= count_a + 1; end if; end process; led(2) <= count_a(CWIDTH_A-1); -- 125MHz clock process(clkin_125MHz, rstN) begin if (rstN = '0') then count_b <= (others => '0'); elsif rising_edge(clkin_125MHz) then count_b <= count_b + 1; end if; end process; led(3) <= not count_b(CWIDTH_B-1); -- ------------------------------------------------------------ -- Unused outputs -- ------------------------------------------------------------ -- -- Flash select flash_ceN <= 'Z'; -- SSRAM controls ssram_clk <= 'Z'; ssram_ceN <= 'Z'; ssram_beN <= (others => 'Z'); -- MAX II select max2_csN <= 'Z'; -- LCD select lcd_csN <= '1'; -- Common controls fsml_oeN <= 'Z'; fsml_weN <= 'Z'; -- Address/data buses -- * explicitly drive the address/data buses low to avoid -- violating the I/O voltage -- * if the address bus is tri-stated, and the I/O clamping -- diodes are not enabled (the default Quartus setting), -- A0 gets pulled to 4.45V and the other signals get pulled -- to 2.8V. The voltage is limited on the other signals due -- to the clamping diodes on the data bus (FPGA), or on other -- devices (A1 is connected to the SSRAM and Flash). -- fsml_addr <= (others => '0'); fsml_dq <= (others => '0'); -- Ethernet PHY enet_rstN <= '0'; -- hold in reset -- Management I2C interface enet_mdc <= 'Z'; enet_mdio <= 'Z'; -- PHY transciever interface -- enet_tx <= '0'; -- PCIe transciever interface -- pcie_tx <= '0'; -- EPCS epcs_clk <= 'Z'; epcs_csN <= 'Z'; epcs_mosi <= 'Z'; end architecture;

[Altera_Forum]

sorry , I don't know

[Altera_Forum]

If you want something to work right away, you can always make a schematic file, click and drag over an output pin and tie it to VCC. In the pin planner, you'll be able to select the correct voltage for that pin.  

   --- Quote Start ---  Hello,  I am new to quartus and would require help with the pin assignment feature(using pin planner). I have created a certain design. In the design it is required that certain inputs are always high and certain are always low. I thought of connecting the high inputs to VCC and low to ground. But when I wanted to make that assignment I find that the pins which are shown by in the pin planner layout as vcc or ground cannot be accessed in the location column(The place where the pin number is written). Is there any other way I can assign a permanent high or permanent low to the inputs. I am using the Altera Cyclone 3 FPGA starter kit. I would highly appreciate some inputs.  Thanks and Regards Ranjan Banerjee  --- Quote End ---  

[Altera_Forum]

Hello,  

Thanks all for your responses. I have indeed made a schematic and there is an input called rd-enable which I always want to be 1. But I am not able to tie it with Vcc in the pin assignment as that option is not highlighted in the location table(Basically I am not able to choose Vcc or ground from pin assignment table, I dont know why this option does not exist). How can I circumvent it?  Thanks and Regards Ranjan

[Altera_Forum]

You don't "choose vcc", you tie your pin to VCC (click and drag the symbol) and connect it to your pin. Then in the pin editor you find your pin and chose the output, 3.3LVTTL, LVDS, etc.

[Altera_Forum]

Hello rbugalho, 

Thanks, now I got the picture. I will do the change accordingly.

[Altera_Forum]

Hello, 

So I incorporated VCC and GND in my schematic. After compilation when I see the pin finder window, the Vcc and Gnd options do not exist in the pin finder window nodes. So my guess is it(Quartus) implicitly assigned a high logic and Gnd and there is no need to explicitly make the connection to the VCC in schematic to a VCC in the pin diagram. Am I right?   There is also one more thing I wanted to ask. I need outputs to communicate with another device(AD9910 manufactured by Analog Devices). I have a HSMC prototyping board. How do I know which pins in the FPGA correspond to the prototyping board pins. For eg: I require a CMOS 3.3V output. The HSMC data sheet says that it is pin 41 in the HSMC bank. I need to tie one of my outputs to pin 41 of the HSMC board. How do I figure the appropriate pin to be assigned in the pin planner so that pin 41 of the HSMC board(which I have interfaced with the FPGA) will reflect my desired output?  Thanks and Regards Ranjan

[Altera_Forum]

To confirm the pin levels are at VCC or GND, look in the fitter pin report file. 

 Its the .pin file for your project.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   So I incorporated VCC and GND in my schematic. After compilation when I see the pin finder window, the Vcc and Gnd options do not exist in the pin finder window nodes. So my guess is it(Quartus) implicitly assigned a high logic and Gnd and there is no need to explicitly make the connection to the VCC in schematic to a VCC in the pin diagram. Am I right?  --- Quote End ---    Yes. The pin assignment editor only lists PINs, which are the variable input and outputs of your design.  The VCC symbol is not a PIN, it's just a logic constant '1', while the GND symbol is just a logic constant '0'.  There's no actual connection to the VCC or GND pins. Quartus just handles it during synthesis. Ie, consider something like "b_signal = a_signal AND rd_enable". Now that you've set rd_enable to a constant '1', then the "AND" operation is optimized away and it just becomes b_signal = a_signal.     --- Quote Start ---   There is also one more thing I wanted to ask. I need outputs to communicate with another device(AD9910 manufactured by Analog Devices). I have a HSMC prototyping board. How do I know which pins in the FPGA correspond to the prototyping board pins. For eg: I require a CMOS 3.3V output. The HSMC data sheet says that it is pin 41 in the HSMC bank. I need to tie one of my outputs to pin 41 of the HSMC board. How do I figure the appropriate pin to be assigned in the pin planner so that pin 41 of the HSMC board(which I have interfaced with the FPGA) will reflect my desired output?  --- Quote End ---    You need to take a look at both board's documentation and track the signals from the ADC to the HSMC connector to the FPGA.

[Altera_Forum]

Hello rbugalho, 

Thanks for the answers. I have traced the pins to the altera HSMC board and my HSMC prototype board.  Thanks and regards, Ranjan Banerjee