Timing violation occurs for "altctrlclk" block for Cyclone IV FPGA
Design overview:
Only two clock is used output of four input "altclckctrl"
1. One clock is connected to clock controller directly.
2. Other is output of the PLL block.
Note: Quartus II 10.1 is not able to handle two PLL out for clock controller input.
Facing Hold time violation for path of clock which is directly connected
to the clock controller when given frequency constraints on same.
But When constraints not provided then no hold time violation occurs and
Fmax timing report is more than constraint provided earlier.
Can anybody have solution for this I want to put Frequency constraint on clock both clock.
Note: Frequecy of both clock input to controller is same but source are differante.
