problem with a multiprocessor system

[Altera_Forum]

Hello 

 i have built a system with 4 processors, each working independantly of others (an atomous system). When i launch 3 processors at the same time in the nios IDE the system works well. But when i try to launch all at the same time, i remark that there is a least one processor which stops to work. what could be the origin of this problem? please help me

[Altera_Forum]

Single memory chip shared or separate for all cpu? Memory regions are correct? Timing ok? What's the frequency of the system?

[Altera_Forum]

the system work at a frequency of 50 MHz. the four processors share a single SDRAM memory. Memory regions in SDRAM have been correctly separate for each processor.

[Altera_Forum]

What about timing reports? I've tried to use Nios + some additional DMA controllers, written by myself, sharing the same SDRAM chip. I wasn't able to run Nios + more than 4 DMA cores on the same chip. That was Nios + 2 writing to memory DMAs and 2 reading from memory DMAs. Timing report showed, that the interconnect is not able to switch between masters fast enough. My target is Nios + 14 DMA cores (total of 7 streaming channels), so I had to redesign the PCB to use at least on chip per two channels: 1 chip -> 4 DMAs. So 7 channels has 4 chips and Nios has separate SDRAM chip.

[Altera_Forum]

From timequest analyser i see that the system could be run at a maximal frequency of 69,97 MHz. 

a solution coud be the use of on-chip-memory for each processor?

[Altera_Forum]

Yes, if the program is small enough to fit there.

[Altera_Forum]

A simple test would show whether it is SDRAM bandwidth limited - once the code/data is cached lack of bandwidth wouldn't matter. 

 It might be caused by problems exiting reset. You'd need to be certain that the JTAG download (if that is what you are using) isn't asserting the global reset for each cpu.  I've used two cpus, in my case I exposed the nios 'soft reset', loaded all the code from a single image, removed the reset from one cpu and got that cpu to remove the other reset after it had done some global initialisation.  I'm downloading (and controlling things) via a PCIe (slave) -> Avalon master bridge.

[Altera_Forum]

i use a jtag for each processor. So if a reset occurs from a jtag download it will reset only the processor which it is associated. 

As i have said in my first post for 3 processors the system works well but with four the problem occurs...

[Altera_Forum]

--- Quote Start ---  A simple test would show whether it is SDRAM bandwidth limited - once the code/data is cached lack of bandwidth wouldn't matter.  It might be caused by problems exiting reset. You'd need to be certain that the JTAG download (if that is what you are using) isn't asserting the global reset for each cpu.  I've used two cpus, in my case I exposed the nios 'soft reset', loaded all the code from a single image, removed the reset from one cpu and got that cpu to remove the other reset after it had done some global initialisation.  I'm downloading (and controlling things) via a PCIe (slave) -> Avalon master bridge.  --- Quote End ---     Dsl,  please how can i do the test to know if the problem come from a bandwidth limitation?  thank you

[Altera_Forum]

--- Quote Start ---  What about timing reports? I've tried to use Nios + some additional DMA controllers, written by myself, sharing the same SDRAM chip. I wasn't able to run Nios + more than 4 DMA cores on the same chip. That was Nios + 2 writing to memory DMAs and 2 reading from memory DMAs. Timing report showed, that the interconnect is not able to switch between masters fast enough. My target is Nios + 14 DMA cores (total of 7 streaming channels), so I had to redesign the PCB to use at least on chip per two channels: 1 chip -> 4 DMAs. So 7 channels has 4 chips and Nios has separate SDRAM chip.  --- Quote End ---    Socrates,  what parameter(s) of timing report did you observe to know that " the interconnect is not able to switch between masters fast enough"?  Thank you

[Altera_Forum]

The problem may be in using the SDRAM memory. The SDRAM write command does not enable to allocate códido at a different address in SDRAM! Nevertheless, when you use the Flash memory is possible to specify where each part of code will be write in command. Check it!